CD2401 Intel, CD2401 Datasheet - Page 18

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
18
IREQ*[1–3]
IACKOUT*
Table 1.
A/D[15:0]
DATDIR*
BUSCLK
BGOUT*
BGACK*
DATEN*
RESET*
Symbol
BERR*
ADLD*
BGIN*
A[0–7]
AEN*
CLK
BR*
Pin Descriptions (Sheet 2 of 4)
80, 81, 83,
84, 86–95,
21, 23, 24
Number
71–78
97, 98
Pin
100
19
10
12
29
30
28
27
26
7
9
5
6
I/O (OD)
I/O (OD)
I/O (TS)
I/O (TS)
O (TS)
O (TS)
O (TS)
O (TS)
Type
OD
O
O
O
I
I
I
I
INTERRUPT ACKNOWLEDGE OUT*: This output is driven low during interrupt
acknowledge cycles for which no internal interrupt is valid.
INTERRUPT REQUEST* [1–3]: These outputs signal that the CD2401 has a
valid interrupt for modem-lead activity (IREQ*1), transmit activity (IREQ*2), or
receive activity (IREQ*3).
BUS REQUEST*: This output is used to signal to the (open-drain) host
processor or bus arbiter that bus mastership is required by the CD2401.
BUS GRANT IN*: This input indicates that the bus is available after the current
bus master relinquishes the bus.
BUS GRANT OUT*: This output is asserted when BGIN* is low and no internal
Bus Request has been made. A daisy-chain scheme of bus arbitration can be
formed by connecting BGOUT* to BGIN* of the next device in the chain. If a
priority scheme is preferred, bus requests must be prioritized externally and bus
grant routed to the BGIN* of the appropriate device.
BUS GRANT ACKNOWLEDGE*: As an input, this signal is used to determine if
another alternate bus master is in control of the bus. As an output, it signals to
other bus masters that this device is in control of the bus.
BUS ERROR*: If this input becomes active while the CD2401 is a bus master,
the current bus cycle is terminated, the bus relinquished, and an interrupt
generated to indicate the error to the host processor.
ADDRESS [0–7]: When the CD2401 is not a bus master, these pins are inputs
used to determine which registers are being accessed, or which interrupt is
being acknowledged. When ADLD* is low, A[0–7] output address bits 8 through
15 for external latching. When the CD2401 is a bus master, A[0–7] output the
least-significant byte of the transfer address.
ADDRESS/DATA [15:0]: When the CD2401 is not a bus master, these pins
provide the 16-bit data bus for reading and writing to the CD2401 registers.
When ADLD* is low, A/D[0–15] provide the upper address bits for external
latching. When the CD2401 is a bus master, A/D[0–15] provide a multiplexed
address/data bus for reading and writing to system memory.
ADDRESS LOAD*: This is a strobe used to externally latch the upper portion of
the system address bus A[31:8]. While ADLD* is low, address bits 31:16 are
available on A/D[15:0], and address bits 8 through 15 on A[7:0].
ADDRESS ENABLE*: This output is used to output enable the external
address bus drivers during CD2401 DMA cycles.
DATA ENABLE*: This output is active when either the CD2401 is a bus master,
or the CS* and DS* pins are low. It is used to enable the external data bus
buffers during host register read/write operations or during DMA operations. For
operations on 32-bit buses, this signal needs to be gated with A[1] to select the
correct half of the data bus.
DATA DIRECTION*: This output is active when either the CD2401 is a bus
master or the CS* pin is low. DATDIR* is used to control the external data
buffers; when low, the buffers should be enabled in the CD2401 to system bus
direction.
CLOCK: System clock.
BUS CLOCK: This is the system clock (divided by 2) used internally to control
certain bus operations. This pin is driven low during hardware reset.
RESET*: This signal should stay valid for a minimum of 20 ns. The reset state
of the CD2401 is guaranteed at the rising edge of this signal. When RESET* is
removed, the CD2401 also performs a software initialization of its registers.
Description
Datasheet