CD2401 Intel, CD2401 Datasheet - Page 33

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

4.2.5.1
4.2.5.2
4.2.6
Datasheet
Berr
Berr
DMA Receive Registers
A Receive Buffer Address Lower (ARBADRL)
A Receive Buffer Address Upper (ARBADRU)
B Receive Buffer Address Lower (BRBADRL)
B Receive Buffer Address Upper (BRBADRU)
A Buffer Receive Byte Count (ARBCNT)
B Buffer Receive Byte Count (BRBCNT)
A Receive Buffer Status (ARBSTS)
B Receive Buffer Status (BRBSTS)
Receive Current Buffer Address Lower (RCBADRL)
Receive Current Buffer Address Upper (RCBADRU)
DMA Transmit Registers
A Transmit Buffer Address Lower (ATBADRL)
A Transmit Buffer Address Upper (ATBADRU)
B Transmit Buffer Address Lower (BTBADRL)
B Transmit Buffer Address Upper (BTBADRU)
A Buffer Transmit Byte Count (ATBCNT)
B Buffer Transmit Byte Count (BTBCNT)
A Transmit Buffer Status (ATBSTS)
B Transmit Buffer Status (BTBSTS)
Transmit Current Buffer Address Lower (TCBADRL)
Transmit Current Buffer Address Upper (TCBADRU)
Timer Registers
Timer Period Register (TPR)
Receive Timeout Period Register (RTPR)
Receive Timeout Period Register low (RTPRl)
EOF
EOF
EOB
EOB
Binary Value, bits 7:0
UE
0
Multi-Protocol Communications Controller — CD2401
Binary Value
Append
0
0
0
40
42
44
46
48
4A
4C
4D
3C
3E
50
52
54
56
58
5A
5C
5D
38
3A
D8
26
26
42
40
46
44
4A
48
4F
4E
3E
3C
52
50
56
54
5A
58
5F
5E
3A
38
DA
24
25
INTR
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
B
B
W
W
W
B
B
B
B
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W Async
R/W Async
2401own
2401own
33