CD2401 Intel, CD2401 Datasheet - Page 46

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
5.4.3
46
Figure 5. Bus Acquisition Cycle
Figure 6. Data Transfer Timing
DATDIR*
BGACK*
DTACK*
ADLD*
Bus Error Handling
When a bus error is detected during a DMA sequence, the CD2401 terminates the current bus cycle
and relinquishes the bus. Any data transfer in the bus ownership cycle is ignored and the original
conditions are restored. A subsequent retry attempt would start again from these original
conditions.
BGIN*
AEN*
R/W*
BR*
AS*
DS*
bus and gives it up here.
Another component owns the
The CD2401 owns the bus at this point.
High for MEM read
Low for MEM write
High for MEM read
Low for MEM write
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