CD2401 Intel, CD2401 Datasheet - Page 96

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.2.3
96
Register Name: COR2
Register Description: Channel Option 2
Default Value: x’00
Access: Byte Read/Write
Register Name: COR2
Register Description: Channel Option 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 7
IXM
0
Channel Option Register 2 (COR2)
COR2 — HDLC Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COR2 — Asynchronous Mode
FCSApd
TxIBE
Bit 6
Bit 6
Reserved – must be ‘0’.
FCS Append
0 = receive CRC is not passed to host at end of frame.
1 = receive CRC passes to host at end of frame.
Reserved – must be ‘0’.
CRC Inverted
0 = CRC is transmitted inverted (that is, CRC V.41).
1 = CRC is not transmitted inverted (that is, CRC-16).
Reserved – must be ‘0’.
RTS Automatic Output enable
When this bit is set and the channel is enabled, the CD2401 automatically asserts the
RTS* output when it has characters to send. When Idle in Mark mode is selected,
RTS* is asserted prior to opening flags and remains asserted until after a closing flag
has been transmitted.
CTS Automatic Enable
This bit enables the CTS* input to be used as the automatic transmitter enable/dis-
able. If enabled, CTS* is checked before frame transmission starts.
DSR Automatic Enable
This bit enables the DSR* input as the automatic receiver enable/disable. If enabled,
DSR* is checked at the beginning of each received frame.
Bit 5
ETC
Bit 5
0
CRCNinv
Bit 4
Bit 4
0
Bit 3
RLM
Bit 3
0
RtsAO
RtsAO
Bit 2
Bit 2
Motorola Hex Address: x’17
Motorola Hex Address: x’17
CtsAE
CtsAE
Bit 1
Bit 1
Intel Hex Address: x’14
Intel Hex Address: x’14
Datasheet
DsrAE
DsrAE
Bit 0
Bit 0