CD2401 Intel, CD2401 Datasheet - Page 158
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
CD2401
Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
1.CD2401.pdf
(176 pages)
- Current page: 158 of 176
- Download datasheet (918Kb)
CD2401 — Multi-Protocol Communications Controller
9.3
158
AC Electrical Characteristics
Bus Arbitration
DMA Read
DMA Write
Host Read/Write
Symbol
t
PERIOD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
41
42
43
1
2
Period of CLK input (35 MHz maximum)
CLK high to BUSCLK high
CLK high to BUSCLK low
CLK high to BGACK* tristate
BGIN* low to address valid
Address hold after CLK high
CLK high to address tristate
CLK high to ADLD* low
CLK high to ADLD* high
Address setup to ADLD* high
CLK high to AEN*/DATEN*/DATDIR* high
CLK high to AEN*/DATEN*/DATDIR* tristate
CLK high to AEN*/DATEN*/DATDIR* low
Data setup to CLK high
Data hold after CLK high
CLK high to address valid
CLK low to AS* low
CLK high to AS* high
CLK low to DS* low
CLK high to DS* high
DTACK* low setup to CLK high
DTACK* high setup to CLK high (to avoid false termination)
CLK high to data valid
Data hold after CLK high
CLK low to DS* low
CLK high to DS* high
DTACK* low setup to CLK high
DTACK* high setup to CLK high (to avoid false termination)
DS* and CS* low setup to CLK high
Reserved
Reserved
Parameter
1
28.57
MIN
15
10
15
10
50
10
50
0
0
7
Datasheet
MAX
20
20
25
40
25
25
20
25
25
25
30
25
20
25
20
40
25
20
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