CD2401 Intel, CD2401 Datasheet - Page 59

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CD2401

Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
Datasheet
†. R/T is used as a register abbreviation indicating Receive / Transmit followed by the register acronym.
Note: This equation, in general, yields a non-integer result. The nearest integer value, along with the
The receive bit rate generator can also be programmed to act as a DPLL. In that mode, the clock
select and divisor are programmed to be as near as possible to the nominal receive bit rate. Clock
phase adjustments are made by the DPLL logic to lock to the incoming data stream. The receive bit
clock is an optional input to the transmitter. This makes it possible to use the DPLL derived clock
to synchronize the transmit data stream.
Section 5.2
given bit rate is determined with the following equation:
clock source, is the optimum choice for that bit rate. The value loaded in the period register must be
that integer expressed as an 8-bit binary value. The bit-rate error is the difference between the
integer value and the ideal value, expressed as a percentage.
Example 1
This example illustrates programming the bit rate generator at 64 kbps using the internal clock with
a system clock frequency of 35 MHz.
Divisor loaded into R/TBPR
Value loaded into R/TCOR = 00h, to select Clk0
Example 2
This example illustrates programming the bit rate generator at 56,000 bps using external clock.
Again, the system clock frequency is assumed to be at 35 MHz.
The user provides a 1.25-MHz clock on the RXCIN or TXCIN pin.
Divisor loaded into R/TBPR = 21 or 15h
Value loaded into RCOR = 06h, to select External Clock mode
Value loaded into TCOR = C0h, to select External Clock mode
contains examples for programming standard bit rates. The value to be loaded to set a
Bit rate divisor
= 67 or 43h
=
Multi-Protocol Communications Controller — CD2401
Frequency of chosen clock source
-------------------------------------------------------------------------------- - 1
Desired bit rate
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