CD2401 Intel, CD2401 Datasheet - Page 87

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

6.7
Datasheet
Note: A SYN character detect interrupt is generated after the second SYN.
Note: A SYN character detect interrupt is generated after the SYN.
Example 1: (Two SYN mode)
Incoming data:
Data is passed to the host:
Example 2: (Single SYN mode)
Incoming data:
Data is passed to the host as:
Non-8-bit Data Transfers
In Asynchronous mode it is possible to transmit and receive less than 8 bits per character. There
can be 5, 6, 7, or 8 bits per character.
For HDLC mode, 8-bits per character are always transmitted. The CD2401 transmits only byte-
aligned frames. The CD2401 receives HDLC frames using transfers of 8 bits per character, except
for the last character received before the FCS. If this last character is not aligned to an 8-bit
boundary, the ResInd and EOF bits (RISRl[2, 6]) are set.
Junk Junk SYN SYN Data Data Data Data Data Data Data Data
Junk Junk SYN Data Data Data Data Data Data Data Data
Junk Junk SYN SYN Data Data Data Data Data Data Data Data
Junk Junk SYN Data Data Data Data Data Data Data Data Data
Multi-Protocol Communications Controller — CD2401
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