CD2401 Intel, CD2401 Datasheet - Page 57

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.4.7.7
5.4.7.8
Datasheet
Note: When a receive timeout occurs in buffer B, the
The CPU has the following five options:
The required option is written to the REOIR by the CPU to terminate the interrupt. If the terminate
buffer option is chosen, the 2401own bit (A/BRBSTS[0]) should first be cleared by the CPU, or a
new buffer can be supplied by the CPU.
Receive Timeout in Asynchronous DMA Mode
In Asynchronous DMA mode, the only way that the CD2401 releases the ownership is reaching the
end-of-buffer. Receive timeout, or any exceptions, do not release the ownership if end-of-buffer
condition is not met. The following illustrates recommended procedures to handle a receive
timeout in Asynchronous DMA mode.
Scenario 1: Buffer A is currently selected; receive timeout occurs; host wants to continue on.
Recommendation: Do nothing in the receive timeout interrupt service routine.
Scenario 2: Buffer A is currently selected; receive timeout occurs; host no longer requires DMA.
Recommendation: Reset the 2401own bits (A/BRBSTS[0]) and set TermBuff (REOIR[7]) in the
receive timeout interrupt service routine.
Scenario 3: Buffer A is currently used; receive timeout occurs; host wants to start DMA in buffer
B.
Recommendation: Set TermBuff (REOIR[7]) in the receive timeout interrupt service routine. The
CD2401 switches to buffer B.
clears both Ownership Status bits.
The above scenarios apply if buffer B is selected first.
Receive Bus Errors
When a receive bus error interrupt is generated, the RISR and A/BRBSTS registers indicate a bus
error status. The current transfer address is available in RCBADR, the bus error occurred on the
last transfer that started at this address. This means that the actual error address can be up to 16
bytes further in the buffer.
Following a bus-error condition, the CPU can either discontinue the current buffer or retry from the
start of the last transfer. If the buffer is to be discontinued, the number of valid receive bytes can be
calculated by subtracting the starting address (A/BRBADR) from the current address (RCBADR).
The CPU should set the TermBuff bit (REOIR[7]) to terminate this buffer and move to the next.
The transfer that failed to the first buffer, due to the bus error, is still in the receive FIFO and is
transferred to the next buffer following the end of the interrupt.
1. Terminate the buffer.
2. Discard the exception.
3. Terminate the buffer and discard the exception.
4. Continue from the current position in the buffer.
5. Leave an ‘n’-byte gap in the buffer and then continue.
Multi-Protocol Communications Controller — CD2401
CD2401
pops back to buffer A, unless the host
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