CD2401 Intel, CD2401 Datasheet - Page 68

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
6.0
6.1
6.1.1
6.1.2
68
Protocol Processing
HDLC Processing
Frame Check Sequence
FCS is a 16-bit standard computation used in HDLC and defined in ISO 3309. This FCS algorithm
is the same used with the synchronous HDLC operation of the CD2401. The basic characteristics
of the FCS are the following:
Accumulation: FCS computation starts after the opening flag and continues to the closing flag.
Polynomial: The standard polynomial is:
Pre-load: The FCS 16-bit accumulator is preset to all ‘1’s.
Transmit order: The FCS bits are identified as X15 to X0. The most-significant bit is X15, and is
transmitted first. Thus, the first FCS character transmitted has bits X15–X8 in character positions
D1–D8, respectively. The second FCS character has bits X7–X0 in character positions D1–D8,
respectively.
Transmit polarity: Inverted.
Correct remainder: The receiver calculates the entire received frame, including the received FCS
field. If the frame is received error-free, then the correct remainder in the FCS accumulation is ‘F 0
B 8’ (X15 is the leftmost bit).
The FCS can be individually enabled or disabled for the transmitter and receiver.
If enabled for the transmitter, the device appends the FCS on transmitted frames. If disabled, the
device adds no FCS at the end of the frame.
If enabled for the receiver, the device computes the received FCS and reports the results. If the FCS
buffer is enabled, the device includes the 2-byte FCS in the received data presented to the host. If
disabled, the device does not test for received FCS.
HDLC Transmit Mode
The transmitter can be programmed to idle in either flag (01111110) or mark (continuous 1’s) mode
through the idle bit (COR3[3]). When Idle in Mark mode is selected, frame transmission can be
programmed to be pre-pended by a programmable number of pad characters and flags. The pad
character can be selected as either 00 or AA. The pad characters allow the remote receivers phase
locked loop to synchronize quickly to the data. When NRZI encoding is used for Manchester
encoding, the 00 character guarantees a transition every bit time, and the AA character guarantees
exactly one transition per bit time.
x**16 + x**12 + x**5 + 1
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