CD2401 Intel, CD2401 Datasheet - Page 116

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.4
8.4.1
116
Register Name: CCR
Register Description: Channel Command Register – Mode 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel Command and Status Registers
There are two CCR command sets. Mode 1 (bit 7 = 0) commands affect basic channel control. In
Mode 2 (bit 7 = 1), additional commands that control timer functions are available.
Channel Command Register (CCR)
Mode 1
The various command and control bits in this register perform largely independent functions. The
host can assert multiple command bits to achieve the desired effect. The CD2401 clears the register
to ‘1’ after it accepts and acts on a host command. The host must verify that the contents of this
register are ‘0’ prior to issuing a new command. If the Reset All command is issued, all other
commands are ignored. All other combinations are legal, and the order of processing is:
1. Clear channel
2. Initialize channel
3. Enable receive
4. Disable receive
5. Enable transmit
6. Disable transmit
ClrCh
Bit 6
Reserved – must be ‘0’.
Times 1 external clock.
This bit is set to ‘1’ when the user supplies the data clock on TXCIN pin where the
frequency is equal to the transmit data rate. When using the external 1 clock or the
clock from the receiver’s DPLL, the TBPR must be programmed to ‘01h’.
Reserved – must be ‘0’.
Local Loopback Mode
1 = enables the Local Loopback mode
0 = disables the Local Loopback mode
Reserved – must be ‘0’.
InitCh
Bit 5
RstAll
Bit 4
EnTx
Bit 3
DisTx
Bit 2
Motorola Hex Address: x’13
EnRx
Bit 1
Intel Hex Address: x’10
Datasheet
DisRx
Bit 0