CD2401 Intel, CD2401 Datasheet - Page 142

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.6.2
8.6.3
142
Register Name: BERCNT
Register Description: Bus Error Retry Count
Default Value: x’00
Access: Byte Read/Write
Register Name: DMABSTS
Register Description: DMA Buffer Status
Default Value: x’00
Access: Byte Read only
TDAlign
Bit 7
Bit 7
Bit 7
Bits 6:4
Bit 3
Bits 2:0
Bus Error Retry Count (BERCNT) Register
When this register is programmed to ‘0’, any bus error causes a receive/transmit interrupt to be
generated and DMA operations suspended to the buffer in error, until the interrupt is processed by
the host CPU.
When this register contains a non-zero value and when a bus error occurs, the CD2401 retries the
same DMA operation and decrements the register value by one. When the value reaches zero, the
next bus error causes an interrupt, at which time a new count can be loaded by the host CPU.
DMA Buffer Status (DMABSTS) Register
When the CD2401 requires an external buffer for DMA transfers, it checks Ntbuf/Nrbuf bits to
decide which buffer to use. Once the CD2401 starts using the buffer, it toggles Ntbuf/Nrbuf bits
and sets Tbusy/Rbusy bits. At system initialization, Ntbuf and Nrbuf are set to buffer A.
Bit 7
RstApd
Bit 6
Bit 6
Internal DTACK* Synchronization Enable
If external synchronization of DTACK* with BUSCLK is not provided, an internal
synchronization can be enabled by setting this bit (revision M and later).
Reserved – must be ‘0’; reads back as ‘0’.
Byte DMA
0 = The CD2401 attempts to perform 16-bit data transfers whenever possible, and 8-
bit only when necessary (when only one byte is available or odd address boundaries).
1 = The CD2401 always performs 8-bit DMA transfers, the position of the data on
the bus still follows the normal rules relating to the BYTESWAP pin.
Reserved – must be ‘0’; reads back as ‘0’.
Transmit Data Align
This status bit is used internally to manage data alignment in the transmit FIFO.
CrtBuf
Bit 5
Bit 5
Append
Bit 4
Bit 4
Binary Value
Ntbuf
Bit 3
Bit 3
Tbusy
Bit 2
Bit 2
Motorola Hex Address: x’8E
Motorola Hex Address: x’19
Nrbuf
Bit 1
Bit 1
Intel Hex Address: x’8D
Intel Hex Address: x’1A
Datasheet
Rbusy
Bit 0
Bit 0