CD2401 Intel, CD2401 Datasheet - Page 80

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
6.3.3
80
Short-Frame Processing
Short frames in Bisync mode are generally terminated with minimum two bytes of XOFF. The
CD2401 reports these frames as follows:
Frame = SYN SYN STX ENQ FF FF
Reported as:
STX and ENQ are passed to host as data.
CRC Calculation in Bisync Mode
In Bisync mode there are several conditions where the CD2401 varies the way it computes the FCS
or BCC/CRC. Which data is included in the current frame depends on how the previous frame
ended and the transparency in the middle of a frame.
The following illustrations show the point in the current frame where FCS computation begins
based on how the previous frame ended. From the start of a frame when the previous frame ended
in DLE-ITB, the following data streams have CRC computed as:
From the start of a frame when the previous frame did not end in DLE-ITB, the following four data
streams have CRC computed as:
Transition from a non-transparent to a transparent frame:
Within a non-transparent frame:
SYN
SYN
SYN
SYN
SYN
SYN
SYN
SYN
receive CRC error
receive abort
SYN
SYN
SOH
SYN
SYN
SYN
SYN
Data
DLE
DLE
CRC
Data
SOH
Data
SOH
STX
SOH
STX
CRC Begins
DLE
CRC Begins
CRC Begins
Data
Data
Data
STX
Data
Data
Data
CRC
Data
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