CD2401 Intel, CD2401 Datasheet - Page 35

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.0
5.1
5.1.1
Datasheet
Functional Description
Host Interface
The CD2401 is a synchronous device with an asynchronous bus interface. A stable input clock is
required on the CLK pin — nominally 33 MHz. CLK is divided by two internally, and the resulting
signal is an output on the BUSCLK pin. The baud-rate generators and timers are also related to
CLK. The
output signal transitions are related to the edges of the CLK and BUSCLK signals. It is possible,
however, to use the CD2401 in a purely asynchronous bus environment.
The CD2401 can act as either bus master during DMA transfers, or as a bus slave device during
normal host read and write transfers. Both byte and word transfers are supported in each of the Bus
Slave and DMA Bus Master modes.
transfers.
Host Read and Write Cycles
The host read and write cycles begin with the activation of the CS* and DS* signals. The
DATADIR* and DATEN* signals control external data buffers. The falling edge of the DTACK*
signal indicates that the transfer is complete. DTACK* is released when DS* is deasserted. At that
time CS* should also be deasserted. The AS* is not used during slave cycles; it is an output during
DMA transfers.
Note that the following open-drain and tristate outputs should have pull-up resistors attached:
AEN*, AS*, DATADIR*, DATEN*, and DTACK*.
“AC Electrical Characteristics”
Multi-Protocol Communications Controller — CD2401
Figure 2
in
Chapter 9.0
and
Figure 3
shows that many input signal setup and
show the signals involved in these
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