CD2401 Intel, CD2401 Datasheet - Page 39

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.2.3
Datasheet
Figure 4. Interrupt Acknowledge Cycle
A/D[15:0]
R/W*, CS*
DATDIR*
1
DTACK*
IACKIN*
Interrupt vector is always on A/D[7:0].
IREQn*
A[7:0]
DEN*
Groups and Types
There are two general reasons for the CD2401 to request service from the host processor — data
transfer and exceptional conditions. Furthermore, interrupts are grouped into three categories, each
with an associated Interrupt Request signal — IREQ1*, IREQ2*, and IREQ3*.
Group 1 is used only for exceptions. Groups 2 and 3 include both data transfer and exceptions.
Table 2
an interrupt request is encoded into the two least-significant bits of the vector presented on the data
bus during the interrupt acknowledge cycle. The most-significant six bits of the vector come from
the LIVR:
DS*
•
•
•
Group 1 — Modem signal change/timer events
Group 2 — Transmit interrupts
Group 3 — Receive interrupts
shows the possible causes of transmit and receive interrupt service requests. The cause of
Multi-Protocol Communications Controller — CD2401
CD2401 SAMPLES
ADRESS BUS
VECTOR
1
1 CLOCK
DELAY
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