CD2401 Intel, CD2401 Datasheet - Page 113

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.2.13
8.3
8.3.1
8.3.1.1
Datasheet
Register Name: CPSR
Register Description: CRC Polynomial Select
Default Value: x’00
Access: Byte Read/Write
Register Name: RBPR
Register Description: Receive Bit-Rate Period
Default Value: x’81
Access: Byte Read/Write
Bit 7
Bit 7
0
Reception of an HDLC frame can be qualified with a matched 1- or 2-byte address field either as
four 1-byte alternatives or two 2-byte alternatives. Control of how the RFARs are used for address
recognition is detailed in the description of the CORs (see
CRC Polynomial Select Register (CPSR)
Bits 7:1
Bit 0
Bit Rate and Clock Option Registers
Receive Bit Rate Generator Registers
Receive Bit Rate Period Register (RBPR)
This register contains the preload value for the receive bit rate counter. When using an internal
clock option or an n-times external clock, the preload value, in conjunction with the receiver clock
source chosen, determines the receive bit rate. If a 1 external clock is used, a value of 01h must be
loaded in the RBPR.
Bit 6
Bit 6
0
Reserved – must be ‘0’.
Polynomial select
0 = CRC V.41 polynomial (normally used for HDLC protocol and preset to 1’s)
x**16 + x**12 + x**5 + 1
1= CRC-16 polynomial (generally used for Bisync but will work in HDLC mode,
preset to 0’s)
x**16 + x**15 + x**2 + 1
Bit 5
Bit 5
0
Receive Bit Rate Period (Divisor)
Bit 4
Bit 4
0
Multi-Protocol Communications Controller — CD2401
Bit 3
Bit 3
0
page 94
Bit 2
Bit 2
0
through
Motorola Hex Address: x’D6
Motorola Hex Address: x’CB
Bit 1
Bit 1
page
Intel Hex Address: x’D4
Intel Hex Address: x’C9
0
108).
Bit 0
Poly
Bit 0
113