MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 82

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.1.2
Read: Anytime.
Write: Never, writes to this register have no effect.
2.3.2.1.3
Read: Anytime.
Write: Anytime.
82
Module Base + 0x0001
Module Base + 0x0002
DDRT[7:0]
PTIT[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRT7
PTIT7
Port T Input Register — This register always reads back the status of the associated pins. This can also be
used to detect overload or short circuit conditions on output pins.
Data Direction Port T — This register configures each port T pin as either input or output.
The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM module port
associated with an enabled output compare. In these cases the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer input capture always monitors the state of the pin.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT
—
0
7
7
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
or PTIT registers, when changing the DDRT register.
= Unimplemented or Reserved
DDRT6
PTIT6
—
0
6
6
Figure 2-5. Port T Data Direction Register (DDRT)
Figure 2-4. Port T Input Register (PTIT)
Table 2-5. DDRT Field Descriptions
DDRT5
Table 2-4. PTIT Field Descriptions
PTIT5
MC9S12C-Family / MC9S12GC-Family
—
0
5
5
DDRT4
PTIT4
Rev 01.24
—
0
4
4
Description
Description
DDRT3
PTIT3
—
0
3
3
DDRT2
PTIT2
—
0
2
2
DDRT1
Freescale Semiconductor
PTIT1
—
0
1
1
DDRT0
PTIT0
—
0
0
0