MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 109

MC9S12C128VFU

Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12C128VFU

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

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Chapter 3
Module Mapping Control (MMCV4) Block Description
3.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core
platform.
The block diagram of the MMC is shown in
The MMC is the sub-module which controls memory map assignment and selection of internal resources
and external space. Internal buses between the core and memories and between the core and peripherals is
controlled in this module. The memory expansion is generated in this module.
Freescale Semiconductor
EBI ALTERNATE WRITE DATA BUS
EBI ALTERNATE READ DATA BUS
EBI ALTERNATE ADDRESS BUS
READ & WRITE ENABLES
CPU WRITE DATA BUS
CPU READ DATA BUS
MODE INFORMATION
CPU ADDRESS BUS
BDM_UNSECURE
CLOCKS, RESET
CPU CONTROL
Introduction
STOP, WAIT
SECURE
REGISTERS
MC9S12C-Family / MC9S12GC-Family
Figure 3-1. MMC Block Diagram
Figure
BUS CONTROL
SECURITY
Rev 01.24
MMC
3-1.
INTERNAL MEMORY
ADDRESS DECODE
EXPANSION
ALTERNATE WRITE DATA BUS (BDM)
ALTERNATE READ DATA BUS (BDM)
ALTERNATE ADDRESS BUS (BDM)
MEMORY SPACE SELECT(S)
PERIPHERAL SELECT
PORT K INTERFACE
CORE SELECT (S)
MMC_SECURE
109

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