MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 435

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 15
Timer Module (TIM16B8CV1) Block Description
15.1
The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage
programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The
input capture function is used to detect a selected transition edge and record the time. The output compare
function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator
is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares
timer channel 7 when in event mode.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
15.1.1
The TIM16B8CV1 includes these distinctive features:
Freescale Semiconductor
Version
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•
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Number
01.03
01.04
01.05
Eight input capture/output compare channels.
Clock prescaling.
16-bit counter.
16-bit pulse accumulator.
Introduction
Features
Revision Dates
05 May 2010
06 Feb 2006
08 July 2008
05 May 2010
08 July 2008
06 Feb 2006
Effective
Date
MC9S12C-Family / MC9S12GC-Family
Table 15-1. Revision History
S. Chinnam
S. Chinnam
Ame Wang
Author
Rev 01.24
Corrected the type at 0x006 and later in the document
from TSCR2 and TSCR1
Revised flag clearing procedure, whereby TEN bit must be
set when clearing flags.
-in 15.3.2.8/15-446,add
-in 15.3.2.11/15-450,TCRE bit description part,add Note
-in 15.4.3/15-459,add
Description of Changes
Figure 15-29
Table 15-11
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