MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 200

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.2
200
Module Base + 0x0021
Starting address location affected by INITRG register setting.
Reset
Field
TRG
CF
3:0
AF
BF
7
6
5
W
R
Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger A did not match
1 Trigger A match
Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger B did not match
1 Trigger B match
Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This
bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Comparator C did not match
1 Comparator C match
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown
Section 7.4.2.5, “Trigger
AF
Debug Status and Control Register (DBGSC)
0
7
= Unimplemented or Reserved
Figure 7-5. Debug Status and Control Register (DBGSC)
BF
0
6
TRG Value
Modes,” for more detail.
Table 7-5. DBGSC Field Descriptions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1111
Table 7-6. Trigger Mode Encoding
MC9S12C-Family / MC9S12GC-Family
↓
CF
0
5
Rev 01.24
0
0
4
A and Not B (full mode)
Description
A then event only B
A and B (full mode)
(Defaults to A only)
Outside range
Event only B
Inside range
Reserved
Meaning
A then B
A only
A or B
0
3
0
2
TRG
Freescale Semiconductor
0
1
Table
7-6. See
0
0