MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 171

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
BDMACT
ENBDM
ENTAG
TRACE
Field
SDV
7
6
5
4
3
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
Tagging Enable — This bit indicates whether instruction tagging in enabled or disabled. It is set when the
TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag
function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active.
0 Tagging not enabled or BDM active
1 Tagging enabled
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a firmware read command or after data has been received as part of a firmware write command. It is
cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM
firmware to control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware
command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are
executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete.
Table 6-2. BDMSTS Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Chapter 6 Background Debug Module (BDMV4) Block Description
Description
171