MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 288

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.1.2
10.1.3
The basic features of the MSCAN are as follows:
1. Depending on the actual bit timing and the clock jitter of the PLL.
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Wake-Up Interrupt Req.
Transmit Interrupt Req.
Receive Interrupt Req.
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Errors Interrupt Req.
Implementation of the CAN protocol — Version 2.0A/B
— Standard and extended data frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbps
— Support for remote frames
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization using a “local priority” concept
Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or eight 8-bit filters
Programmable wakeup functionality with integrated low-pass filter
Programmable loopback mode supports self-test operation
Programmable listen-only mode for monitoring of CAN bus
Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
Programmable MSCAN clock source either bus clock or oscillator clock
Internal timer for time-stamping of received and transmitted messages
Three low-power modes: sleep, power down, and MSCAN enable
Global initialization of configuration registers
Oscillator Clock
Block Diagram
Features
Bus Clock
MSCAN
Figure 10-1. MSCAN Block Diagram
MUX
MC9S12C-Family / MC9S12GC-Family
Configuration
CANCLK
Registers
Control
Status
and
1
Rev 01.24
Presc.
Tq Clk
Wake-Up
Low Pass Filter
Message
Buffering
Receive/
Transmit
Filtering
Engine
and
Freescale Semiconductor
RXCAN
TXCAN