MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 377

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

12.4.2.5
The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They
are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two
registers, a duty register and a period register as shown in the block diagram in
PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period register resets the counter and the
output flip-flop as shown in
duty register to the associated registers as described in
counter counts from 0 to the value in the period register – 1.
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
As an example of a left aligned output, consider the following case:
Freescale Semiconductor
•
•
PWMx frequency = clock (A, B, SA, or SB) / PWMPERx
PWMx duty cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
— Polarity = 1 (PPOLx = 1)
Clock source = bus clock, where bus clock = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx frequency = 10 MHz/4 = 2.5 MHz
PWMx period = 400 ns
PWMx duty cycle = 3/4 *100% = 75%
Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty cycle = [PWMDTYx / PWMPERx] * 100%
Left Aligned Outputs
Changing the PWM output mode from left aligned output to center aligned
output (or vice versa) while channels are operating can cause irregularities
in the PWM output. It is recommended to program the output mode before
enabling the PWM channel.
PPOLx = 0
PPOLx = 1
Figure 12-36. PWM Left Aligned Output Waveform
Figure 12-35
MC9S12C-Family / MC9S12GC-Family
PWMDTYx
as well as performing a load from the double buffer period and
Rev 01.24
NOTE
Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Period = PWMPERx
Section 12.4.2.3, “PWM Period and Duty.”
Figure
12-35. When the
The
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