MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 303

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

10.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Read: Anytime
Write: Anytime when not in initialization mode
Freescale Semiconductor
Module Base + 0x0007
TXEIE[2:0]
TXE[2:0]
Field
Field
2:0
2:0
Reset:
W
R
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge Register
is cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
Transmitter Empty Interrupt Enable
0 No interrupt request is generated from this event.
1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt
MSCAN Transmitter Interrupt Enable Register (CANTIER)
request.
The CANTIER register is held in the reset state when the initialization mode
is active (INITRQ = 1 and INITAK = 1). This register is writable when not
in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
7
Figure 10-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register
= Unimplemented
Table 10-11. CANTFLG Register Field Descriptions
Table 10-12. CANTIER Register Field Descriptions
6
0
0
MC9S12C-Family / MC9S12GC-Family
Section 10.3.2.2, “MSCAN Control Register 1
0
0
5
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
NOTE
4
0
0
Description
Description
0
0
3
Section 10.3.2.10, “MSCAN Transmitter
TXEIE2
(CANTARQ)”). If not masked, a
2
0
(CANCTL1)”) the TXEx flags
TXEIE1
(CANTARQ)”).
0
1
TXEIE0
0
0
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