MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 104

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.4
Each pin can act as general purpose I/O. In addition the pin can act as an output from a peripheral module
or an input to a peripheral module.
A set of configuration registers is common to all ports. All registers can be written at any time, however a
specific configuration might not become active.
Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-
pull output.
2.4.1
2.4.1.1
This register holds the value driven out to the pin if the port is used as a general purpose I/O. Writing to
this register has only an effect on the pin if the port is used as general purpose output. When reading this
address, the value of the pins are returned if the data direction register bits are set to 0.
If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent
of any other configuration
2.4.1.2
This is a read-only register and always returns the value of the pin
2.4.1.3
This register defines whether the pin is used as an input or an output. If a peripheral module controls the
pin the contents of the data direction register is ignored
104
Functional Description
Registers
I/O Register
Input Register
Data Direction Register
(Figure
Figure 2-46. Illustration of I/O Pin Functionality
Module
DDR
PTI
PT
2-46).
MC9S12C-Family / MC9S12GC-Family
Data Out
Output Enable
Module Enable
0
1
Rev 01.24
0
1
0
1
(Figure
2-46).
(Figure
PAD
2-46).
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