MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 356

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
12.3.2.4
This register selects the prescale clock source for clocks A and B independently.
Read: anytime
Write: anytime
356
Module Base + 0x0003
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
Reset
Field
5
4
3
2
1
0
W
R
Pulse Width Channel 5 Clock Select
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
Pulse Width Channel 4 Clock Select
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
PWM Prescale Clock Select Register (PWMPRCLK)
0
0
7
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
Figure 12-6. PWM Prescaler Clock Select Register (PWMPRCLK)
= Unimplemented or Reserved
PCKB2
0
6
Table 12-4. PWMCLK Field Descriptions
PCKB1
MC9S12C-Family / MC9S12GC-Family
0
5
PCKB0
Rev 01.24
NOTE
0
4
Description
0
0
3
PCKA2
0
2
PCKA1
Freescale Semiconductor
0
1
PCKA0
0
0