MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 239

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.3.2.8
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
Freescale Semiconductor
Module Base + 0x0008
CC[2:0]
FIFOR
Reset
Field
2–0
4
W
R
FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
0 No over run has occurred
1 An over run condition exists
Conversion Counter — These 3 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. For example, CC2 = 1,
CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-
FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion
sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps
around when its maximum value is reached.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-2) clears the
conversion counter even if FIFO=1.
Reserved Register (ATDTEST0)
U
1
7
Writing to this registers when in special modes can alter functionality.
A) Write “1” to FIFOR
B) Start a new conversion sequence (write to ATDCTL5 or external trigger)
= Unimplemented or Reserved
U
0
6
Table 8-13. ATDSTAT0 Field Descriptions (continued)
Figure 8-10. Reserved Register (ATDTEST0)
MC9S12C-Family / MC9S12GC-Family
U
0
5
Rev 01.24
NOTE
U
0
4
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
Description
U
0
3
U
0
2
U
0
1
U
0
0
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