MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 401

MC9S12C128VFU

Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12C128VFU

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

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13.4.4.2
During an SCI reception, the receive shift register shifts a frame in from the Rx input signal. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
13.4.4.3
The receiver samples the Rx input signal at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see
synchronized:
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-11
Freescale Semiconductor
RT CLOCK COUNT
RESET RT CLOCK
Rx Input Signal
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
RT CLOCK
SAMPLES
summarizes the results of the start bit verification samples.
Character Reception
Data Sampling
1
RT3, RT5, and RT7 Samples
1
1
1
1
000
001
010
011
QUALIFICATION
1
Figure 13-13. Receiver Data Sampling
START BIT
1
Table 13-11. Start Bit Verification
MC9S12C-Family / MC9S12GC-Family
1
0
Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
0
Rev 01.24
VERIFICATION
Start Bit Verification
START BIT
0
Yes
Yes
Yes
No
0
START BIT
SAMPLING
0
DATA
0
0
Noise Flag
0
1
1
0
Figure
13-13) is re-
LSB
401

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