MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 347

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 12
Pulse-Width Modulator (PWM8B6CV1) Block Description
12.1
The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6CV1
module contains the basic features from the HC11 with some of the enhancements incorporated on the
HC12, that is center aligned output mode and four available clock sources. The PWM8B6CV1 module has
six channels with independent control of left and center aligned outputs on each channel.
Each of the six PWM channels has a programmable period and duty cycle as well as a dedicated counter.
A flexible clock select scheme allows a total of four different clock sources to be used with the counters.
Each of the modulators can create independent continuous waveforms with software-selectable duty rates
from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
12.1.1
12.1.2
There is a software programmable option for low power consumption in wait mode that disables the input
clock to the prescaler.
In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is
useful for emulation.
Freescale Semiconductor
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Six independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches 0) or when the channel is disabled.
Programmable center or left aligned outputs on individual channels
Six 8-bit channel or three 16-bit channel PWM resolution
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies.
Programmable clock select logic
Emergency shutdown
Introduction
Features
Modes of Operation
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
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