MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 148

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.2.13
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to
this register have no effect.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
4.3.2.14
Read: See individual bit descriptions below
Write: See individual bit descriptions below
148
Module Base + 0x000F
Starting address location affected by INITRG register setting.
Module Base + 0x001E
Starting address location affected by INITRG register setting.
IRQEN
Field
IRQE
7
6
Reset
Reset
W
W
R
R
IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal and Emulation modes: read anytime, write once
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
External IRQ Enable
Normal, emulation, and special modes: read or write anytime
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
Note: When IRQEN = 0, the edge detect latch is disabled.
Reserved Register
IRQ Control Register (IRQCR)
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
IRQE
7
0
0
7
0
= Unimplemented or Reserved
= Unimplemented or Reserved
IRQEN
6
0
0
6
1
Figure 4-18. IRQ Control Register (IRQCR)
Table 4-12. IRQCR Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Figure 4-17. Reserved Register
5
0
0
5
0
0
Rev 01.24
0
0
0
0
Description
4
4
0
0
0
0
3
3
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0