MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 212

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.4
This section provides a complete functional description of the DBG module. The DBG module can be
configured to run in either of two modes, BKP or DBG. BKP mode is enabled by setting BKABEN in
DBGC2. DBG mode is enabled by setting DBGEN in DBGC1. Setting BKABEN in DBGC2 overrides the
DBGEN in DBGC1 and prevents DBG mode. If the part is in secure mode, DBG mode cannot be enabled.
7.4.1
In BKP mode, the DBG will be fully backwards compatible with the existing BKP_ST12_A module. The
DBGC2 register has four additional bits that were not available on existing BKP_ST12_A modules. As
long as these bits are written to either all 1s or all 0s, they should be transparent to the user. All 1s would
enable comparator C to be used as a breakpoint, but tagging would be enabled. The match address register
would be all 0s if not modified by the user. Therefore, code executing at address 0x0000 would have to
occur before a breakpoint based on comparator C would happen.
The DBG module in BKP mode supports two modes of operation: dual address mode and full breakpoint
mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints
occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just
before the tagged instruction executes. The action taken upon a successful match can be to either place the
CPU in background debug mode or to initiate a software interrupt.
The breakpoint can operate in dual address mode or full breakpoint mode. Each of these modes is
discussed in the subsections below.
7.4.1.1
When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the
system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in
212
Module Base + 0x002F
Starting address location affected by INITRG register setting.
Reset
Field
15:0
15:0
W
R
Functional Description
DBG Operating in BKP Mode
Bit 7
Comparator B Compare Bits — The comparator B compare bits control whether comparator B compares the
address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0, compares to data if in Full mode
1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
Dual Address Mode
0
7
Figure 7-21. Debug Comparator B Register Low (DBGCBL)
Bit 6
0
6
Table 7-23. DBGCB Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Bit 5
0
5
Rev 01.24
Bit 4
0
4
Description
Bit 3
0
3
Table
Bit 2
0
2
7-20.
Freescale Semiconductor
Bit 1
0
1
Bit 0
0
0