MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 206
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MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128VFUE
Manufacturer:
Freescale
Quantity:
38 000
Company:
Part Number:
MC9S12C128VFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.8
1. In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s.
2. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
206
Module Base + 0x0029
Starting address location affected by INITRG register setting.
RWCEN
BKCEN
TAGAB
Reset
TAGC
Field
RWC
4
3
2
1
0
W
R
BKAMBH
Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Breakpoint Comparator C Enable Bit — This bit enables the breakpoint capability using comparator C.
0 Comparator C disabled for breakpoint
1 Comparator C enabled for breakpoint
Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode.
Comparator C Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for comparator C. RWCEN is not useful for tagged breakpoints.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Debug Control Register 3 (DBGC3)
0
7
(1)
BKAMBL
0
6
Table 7-14. DBGC2 Field Descriptions (continued)
Figure 7-14. Debug Control Register 3 (DBGC3)
1
BKBMBH
MC9S12C-Family / MC9S12GC-Family
0
5
(2)
BKBMBL
Rev 01.24
0
4
Description
2
RWAEN
0
3
RWA
0
2
RWBEN
Freescale Semiconductor
0
1
RWB
0
0
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