IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 98

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

8.4
Intel NetStructure
TPS
98
®
Electronic Keying
IXB2850 boards, following the PICMG 3.0 specification, supports the Electronic Keying
(E-Keying) mechanism on the following backplane interfaces:
Since the BMC does not control access to these interfaces directly, it performs E-Keying
operations via the NPU, which can set up backplane interfaces. To allow this
cooperation and fully support the E-Keying functionality, the BMC maintains an E-
Keying Status Word and forwards E-Keying IPMI messages to the NPU.
Cooperation between the BMC and NPU can be divided into the following phases:
Phase 1
In phase 1, the NPU is not powered on and the board backplane interfaces are disabled.
If the BMC receives a Set Port State or Bus Resource Control command in this
phase, it modifies the
E-Keying Status Word accordingly. Since the NPU is not operational, no other action is
performed.
If an IXB2850 board works without the chassis and the ShMC is not present, then the
BMC modifies the E-Keying Status Word to indicate that all ports belong to the point-to-
point interfaces (base interface, fabric interface and update interface) are enabled.
Phase 2
In phase 2, the NPU runs Boot Monitor or diagnostics code. In this phase, the NPU is
not able to receive IPMI messages that are sent asynchronously by the BMC. It can
only send a request message to the BMC and receive a response. In this phase, only
the NPU can start message exchange between the NPU and BMC.
diagram illustrating the cooperation between the NPU and BMC in this phase.
• Fabric interface
• Base interface
• Update interface
• Clock interface
• Phase 1 – NPU not powered
• Phase 2 – NPU runs Boot Monitor or diagnostics code
• Phase 3 – NPU runs the Linux operating system
IXB2850 Packet Processing Boards
IXB2850—Board Management Controller Firmware
Document Number: 05-2443-006
Figure 31
is a UML
January 2007