IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 57

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Hardware Management—IXB2850
Table 22.
January 2007
Document Number: 05-2443-006
Processor SDR format (Continued)
IXB2850 boards contain two processors acting as sensors, the BMC and the NPU. The
board can also support a PrPMC (for example, an Adjunct Processor) acting as a sensor.
Byte(s)
13
14
15:16
17:18
19:20
21
22
23
24:25
26
27
28
29
30
31
32
33:+N
Field Name
Sensor Type
Event / Reading Type Code
Assertion Event Mask
Deassertion Event Mask
Discrete Reading Mask
Sensor Units 1
Sensor Units 2 - Base Unit
Sensor Units 2 - Modifier Unit
Sensor Record Sharing
Positive-going Threshold
Hysteresis value
Negative-going Threshold
Hysteresis value
reserved
reserved
reserved
OEM
ID String Type/Length Code
ID String Bytes
Value
07h
70h
0007h
0000h
0000h
C0h
00h
00h
00h
00h
00h
00h
00h
00h
Comments
Processor
OEM Discrete with the following defined offsets:
Three bit mask
No deassertion events
Reading not supported
None
Unspecified
Unused
No sharing
No Threshold Hysteresis
No Threshold Hysteresis
OEM information
Intel NetStructure
• 00h – Booting
• 01h – POST
• 02h – Diagnostics
• 7:5 – reserved
• 4:1 – Processor ID:
• 0:0 – Virtual Console:
- 00h BMC
- 01h NPU#1
- 02h NPU#2
- 03h PrPMC (for example, an Adjunct Processor)
- 0b Not supported
- 1b Supported
®
IXB2850 Packet Processing Boards
TPS
57