IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 31

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Hardware Overview—IXB2850
3.3.1
Figure 11.
Note:
January 2007
Document Number: 05-2443-006
Ethernet Packet Formats Over the Backplane
To ensure continuity of data flow to both FIC and baseboard IXF1104 MAC devices, “in-
band addressing” is implemented in the Fork FPGA. This addressing scheme enables
the transmission of data to, and the reception of data from, the two devices connected
to the Fork FPGA. Each data packet transmitted between the Network Processor (NP)
and the Fork FPGA includes an additional quad word as a header. In the transmit (TX)
direction, the header contains information about the destination device of the packet.
In the Receive (RX) direction, the header contains information about the source device.
In the TX direction, the NP creates the header and adds it at the beginning of each data
packet. The addition of the quad word header does not modify the checksum that is
transmitted in the packet. The Fork FPGA is responsible for removing the addressing
header from the data packet before sending the packet to the appropriate device.
The header has a very simple structure since only one bit is needed to specify the
destination device. See
In-band addressing header format
Figure 12
The Fork FPGA operates with the Baseboard IXF1104 and FIC card in SPI-3, 4 x 8 bit
SPHY mode. The 4 x 8 bit mode has been implemented to avoid the blocking of data
flow from one device by the blockage of data on the other device. The Fork FPGA has
2048 bytes buffers (in the Fork FPGA) for each of the 8 lanes used by the Baseboard
IXF1104 and FIC. Data received from the MAC on the FIC card is converted to SPI-3
MPHY 32-bit mode for the SPI-3/4 Bridge.
In firmware version 1B2 and later, the addition of the 64-bit prefix, enabled by default,
can be disabled when loading the baseboard driver by including the
noFabricPrepend=1 parameter on the command line as follows:
bb_linux_drv.ko noFabricPrepend=1
• In the transmit direction, the Fork FPGA receives data with the addressing header
• In the RX direction, the Fork FPGA is responsible for adding the header to each
from the SPI-3/4 Bridge and transmits it to the Baseboard IXF1104 or FIC without
the header.
packet received from the Baseboard IXF1104 MAC or the FIC card.
| LW## | Oct 0 | Oct 1 | Oct 2 | Oct 3 |
----------------------------------------
| LW00 |
----------------------------------------
| LW01 |
----------------------------------------
| LW02 |
----------------------------------------
| LW03 | ...
shows operation in the transmit (Tx) and receive (Rx) directions:
0x00 | 0x00
0x00 | 0x00
0x00 | 0x20
Figure
| 0x00
| 0x00
| 0xaa
11.
| 0x01
| 0x00
| 0xbb
|
|
|
|
Prepended Header:
0x00000000 = Baseboard IXF1104 Packet
0x00000001 = FIC Packet (as shown)
Reserved:
Always 0x00000000
In-band Addressing
L2 Header
.
Intel NetStructure
Header
®
IXB2850 Packet Processing Boards
insmod
TPS
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