IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 109

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Network Processor Firmware—IXB2850
Table 49.
9.3
January 2007
Document Number: 05-2443-006
NPU boot configuration parameters (Continued)
The Boot Configuration parameters can be changed using dedicated Boot Monitor
commands. The BMC and ShMC are also able to change these parameters via a
dedicated OEM FRU record.
Initial Loader
The Initial Loader occupies the first sector (or sectors) of flash memory associated with
a particular processor, that is, the boot sector. The boot sector must be locked (write-
protected) to avoid the possibility that a user accidentally overwrites the boot sector
with an incorrect image, which would render the board unusable and requires
reparation with hardware tools such as a JTAG flash programmer.
The Initial Loader is the first code that the processor executes from flash after it is
released from the reset state (note that the BMC controls reset of the NPU). This code
performs the following actions:
Parameter
Debug Ethernet
IP configuration
Base Interface #1 †
IP configuration type
Base Interface #1 †
IP configuration
Base Interface #2 †
IP configuration type
Base Interface #2 †
IP configuration
Run-time image
searching sequence
† By default, RedBoot* routes the Intel
and the baseboard PHYs to base interfaces. See
• Slow port initialization
• Slow port DIP switch detection (allows executing alternate boot code such as
• PLL configuration (DRAM, SRAM and Advanced Peripheral Bus [APB], an internal
• NPU internal UART initialization
• GPIO initialization
• One of the Boot Monitor codes is selected and executed from flash
VxWorks* boot)
bus used for accessing UART, timers, GPIOs, slow port, etc.)
Description
The static IP configuration for debug Ethernet interface. The following information
is stored here:
A flag indicating the type of IP configuration used for the base interface #1 during
run-time image loading. This flag can have one of two values:
The static IP configuration for base interface #1. The following information is
stored here:
A flag indicating the type of IP configuration used for the base interface #2 during
run-time image loading. This flag can have one of two values:
The static IP configuration for base interface #2. The following information is
stored here:
A script containing a set of commands that are executed by the Boot Manager to
load the run-time image for the NPU.
• IP address
• Subnet mask
• Default gateway
• automatic – IP configuration is obtained via the BOOTP protocol
• static – IP configuration stored as a boot configuration parameter is used
• IP address
• Subnet mask
• Default gateway
• automatic – IP configuration is obtained via the BOOTP protocol
• static – IP configuration stored as a boot configuration parameter is used
• IP address
• Subnet mask
• Default gateway
®
82546 Dual Port Gigabit Ethernet Controller via the crosspoint switch
Figure 7, “IXB2850 board block diagram” on page
Intel NetStructure
®
IXB2850 Packet Processing Boards
26.
TPS
109