IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 228

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

B.1.16
B.1.17
Intel NetStructure
TPS
228
®
Media Traffic POST
The test performs MAC/Framer and PHY/Serdes initialization and starts the microcode
responsible for receiving and transmitting frames. During system loopback test, the
microengine sends a frame with a checksum, then receives a frame on the same
interface. The following devices are tested during the Media POST:
The test cases presented in the following table are performed for:
Telecom Clock POST
The Telecom Clock POST performs Telecom Clocks (Zarlink*) functionality test. This
test generates known frequencies and verifies if the Zarlink synchronies with the
reference clock. The tests cases presented in the following table are executed.
Test ID
07h
08h
09h
Test ID
00h
01h
02h
03h
04h
Test ID
00h
01h
02h
03h
04h
• SPI-3/4 Bridge and Fork FPGA
• Baseboard MAC and PHY
• FIC MAC
• Quad Gigabit Ethernet Mezzanine Card MAC and PHY
• MMC#1devices (not applicable to IXB2850 boards)
• MMC#2 devices (Quad Gigabit Ethernet Mezzanine Card)
• Baseboard devices
• FIC devices
IXB2850 Packet Processing Boards
Description
Registers write/read test for PHY/Serdes ports
Registers default values test for MIC devices
Registers write/read test for MIC devices
Description
MAC/Framer device configuration
MAC/Framer port configuration
Traffic test on system loopback on MAC/Framer ports
PHY/Serdes port configuration
Traffic test on system loopback on PHY/Serdes ports
Description
Telecom Clock device board presence checking
2.048 MHz frequency test
19.44 MHz frequency test
8 kHz frequency test
1.544 MHz frequency test
Document Number: 05-2443-006
IXB2850—Power On Self Test
January 2007