IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 97

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Board Management Controller Firmware—IXB2850
Table 38.
8.3
8.3.1
8.3.2
January 2007
Document Number: 05-2443-006
Send message response format (Continued)
Communications with Other Processors
The BMC can communicate with other IXB2850 CPUs using the following methods:
Serial Connections
An IXB2850 board contains a number of serial lines that connect the BMC with other
CPUs on the baseboard and extension cards. The BMC can communicate over serial
connections with the following CPUs:
The BMC uses the IPMI protocol for communication with other CPUs over serial
connections.
IPMI commands supported during communication over serial lines.
The encoding of the IPMB packets on a character-based serial interface is performed
and understood by both the BMC and CPU. The encoding follows these rules:
KCS Connection
The PrPMC standard that defines the connectors of the PMC card does not include a
UART connection as one of the mandatory connectors (J1, J2, and J3). The user-
defined fourth connector (J4) can be used as a serial connection between processors on
the baseboard and PMC card. The usage of this connector on the PMC card is vendor-
dependent. The BMC is able to communicate with the CPU on a PMC card that is pin-
compatible with the IXB2850 baseboard.
Vendor-independent communication with the CPU on the PMC card is possible only via
the PCI bus. The BMC supports a KCS interface to allow this kind of connection. The
IPMI protocol is used for communication with the PMC Adjunct Processor over the KSC
interface.
commands supported during communication over the KCS interface.
The Linux operating system running on the PMC card can use the BMC Access module
to communicate with the BMC.
Field
Data 7
Data 8:N
Data N+1
Checksum 2
• Over a UART connection
• Over the KCS interface
• NPU
• Adjunct Processor on the PMC card
• Each byte sent on serial interface consists of two fields (7 bits of data) and 1 bit
• Start/stop bit message marker; if 1, this byte is the first or the last in the IPMB
• 7 data bits; data taken from an IPMB message
start/stop message marker.
packet
Section 8.2, “IPMI Protocol Support” on page 90
Section 8.2, “IPMI Protocol Support” on page 90
Description
Completion Code for the remote message
Data for the remote message
Checksum 2 for the remote message
Checksum 2 for the Send Message command
Intel NetStructure
®
describes all IPMI
IXB2850 Packet Processing Boards
describes in detail all the
TPS
97