IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet
IXB28504XGBEFS
Specifications of IXB28504XGBEFS
IXB28504XGBEFS Summary of contents
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... Intel NetStructure Packet Processing Boards Technical Product Specification January 2007 ® IXB2850 Document Number: 05-2443-006 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Firmware Components ....................................................................................... 82 7.2 Boot Sequence.................................................................................................. 82 7.3 Board Management Controller Firmware Overview ................................................. 84 7.4 Network Processor Firmware Overview ................................................................. 84 8.0 Board Management Controller Firmware.................................................................. 85 8.1 BMC Flash Memory Layout and Content ................................................................ 85 January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 3 ...
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... Local Software Upgrade .................................................................................... 137 11.4 Remote NPU Firmware Upgrade ......................................................................... 151 11.5 Remote BMC Firmware Upgrade......................................................................... 158 12.0 Specifications ........................................................................................................ 161 12.1 IXB28504XGBEFSx Mechanical Specifications ...................................................... 161 12.2 Processor Specification ..................................................................................... 163 12.3 Interface Specification ...................................................................................... 163 12.4 Environmental Specification .............................................................................. 164 12.5 Reliability Specification ..................................................................................... 164 12 ...
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... Board reset circuit.................................................................................................... 40 17 Watchdog timers used by the NPU.............................................................................. 42 18 SDR sensor number format ....................................................................................... 54 19 Sensor map entry building process ............................................................................. 55 20 IXB28504XGBEFSx board front panel.......................................................................... 60 21 Backplane connector locations ................................................................................... 63 22 Zone 1 power and system management connector layout .............................................. 64 23 Zone 2 data transport connector layout....................................................................... 66 24 Zone 2 data transport connector base channel and fabric channel port allocation ...
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... SSU usage model ................................................................................................... 152 44 SSU image upgrade operation .................................................................................. 156 45 Remote upgrade of BMC firmware............................................................................. 160 46 IXB28504xGbEFSx board mechanical layout............................................................... 161 47 Quad Gigabit Ethernet Mezzanine Card (fiber) assembled to baseboard.......................... 162 48 Quad Gigabit Ethernet Mezzanine Card front panel (fiber) ............................................ 162 49 Fabric Interface Card assembled to baseboard............................................................ 162 50 NP/BMC console cable ...
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... Baseboard driver API function summary .................................................................... 269 70 Interpretation of the arg_mode value ....................................................................... 292 71 GbEMAC_Ioctl( ) SET commands and IXF1104 register map......................................... 295 72 GbEMAC_Ioctl( ) GET commands and IXF1104 register map ........................................ 297 January 2007 Document Number: 05-2443-006 1 .......................................... 138 1 .......................................................... 139 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 7 ...
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... December 2005 003 September 2005 002 June 2005 001-01 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 8 Description Updates to coincide with the introduction of new SKUs and the SRA 2.1 software release. In Section 11.3.1, “Local Software Upgrade Procedure”, added a statement to check the Release Notes for a list of the components to be upgraded for a specific release. In Section 11.3.1, “ ...
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... Applicability This Technical Product Specification (TPS) covers the following boards: Product Code IXB28504XGBEFS IXB28504XGBEFSW IXB28504XGBEFSR January 2007 Document Number: 05-2443-006 ® IXB2850 boards are AdvancedTCA* form-factor packet-processing ® core. The IXP2850 contains two integrated Description Board with fiber external interfaces; may contain restricted substances Board with fiber external interfaces ...
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... Boot code, Linux Support Package (LSP), and diagnostics • Device drivers for baseboard and mezzanine cards • Support for Carrier Grade Linux* (CGL) • Support for the Intel® Internet Exchange Architecture Software Development Kit (Intel® IXA SDK) • Front panel I/O 1 ...
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... Base Interface This interface is used to access the AdvancedTCA base interface, which is defined as a 1000BASE-T Ethernet by PICMG 3.0. Ports 0 and 1 of the Intel Gigabit Ethernet Controller together with two PHY 0 and 1 devices are used to connect to the base interface. This interface PICMG 3.1 scenario supported by IXB2850 boards, is used for control traffic only ...
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... The AP Mezzanine Card conforms to the Processor PCI Mezzanine Card (PrPMC) standard, so that a PrPMC module (such as a Pentium module) can be used in the PMC site on an IXB2850 baseboard. A System Clock Generator PMC Mezzanine Card could also be used in this position on the board. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 12 13 ...
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... AdvancedTCA Backplane Base Interface Backplane Access DRAM Module Media Access Module Forwarding NP Quad Gigabit Ethernet Mezzanine Card Gigabit Ethernet Interfaces (Front Panel) Intel NetStructure Fabric Interface ® IXB2850 Packet Processing Boards TPS 13 ...
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... In this case, control traffic is generated/terminated by the Adjunct Processor (AP) Mezzanine Card and is mixed with the data traffic of the network processor in the Media Access Module. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 14 AdvancedTCA Backplane ...
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... AP <-> Other blade Other blade <-> NP January 2007 Document Number: 05-2443-006 AdvancedTCA Backplane Base Interface Backplane Access Module DRAM Media Forwarding Access NP Module Quad Gigabit Ethernet Mezzanine Card Gigabit Ethernet Interfaces (Front Panel) Intel NetStructure Fabric Interface ® IXB2850 Packet Processing Boards TPS 15 ...
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... Getting Started This chapter describes how to configure a system that includes Intel NetStructure IXB2850 boards making it possible to run the IXB2850 firmware. 2.1 System Requirements Verify that your setup matches the requirements given in discrepancies, you will need to address them before proceeding. Table 1. ...
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... Not recommended for normal operation and should only be used for service. J2: 15-16 – ON Can be used temporarily to boot the board when the onboard BMC is damaged. Figure 6 are optional for some development/usage scenarios. for more information. Intel NetStructure Section 12.8.1, for ® IXB2850 Packet Processing Boards TPS 17 ...
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... Configure Fast Ethernet interface by editing the scripts/ifcfg-eth0 Ethernet interface is named eth0. The name of the interface may differ depending on the hardware configuration. # IXB2850-specific DEVICE=eth0 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 18 Gb Ethernet (backplane) console) 10/100 Mb Eth Hub or Switch file. In the following example assumed that Fast IXB2850— ...
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... Configure the serial port parameters in minicom as follows: a. Press Ctrl-A O, select Filenames and paths and specify the script directory (option C): /tftpboot January 2007 Document Number: 05-2443-006 /etc/sysconfig/ file. In the following example assumed that minicom as follows: minicom . /dev/ttyS1 ® Intel NetStructure IXB2850 Packet Processing Boards (v. 2.00.0) is TPS 19 ...
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... Configure the Management TFTP server as follows: 1. Create the /tftpboot 2. Edit the /etc/xinetd.d/tftp service tftp { socket_type = dgram protocol wait user server ® Intel NetStructure IXB2850 Packet Processing Boards TPS 20 ). directory on the Management PC. file: /etc/exports directory on the Management PC. file on the Management PC as follows: = udp = yes = root = /usr/sbin/in.tftpd IXB2850— ...
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... Document Number: 05-2443-006 = 100 2 file, adding the following entries: 600; 7200; is the IXB2850 board’s debug Ethernet address that is the address that the user allocates for the IXB2850 /var/lib/dhcp/dhcpd.leases Intel NetStructure file (the lease database) ® IXB2850 Packet Processing Boards TPS 21 ...
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... Intel NetStructure IXB2850 Packet Processing Boards TPS 22 service startup to init scripts by issuing the following dhcpd /tftpboot/GLC_BOARD_IP_ADDR directory ssu_image /tftpboot/GLC_BOARD_IP_ADDR/glc script in directory: ...
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... The first line in the script above loads the baseboard driver. The baseboard driver operates in one of two modes: with or without the 64-bit prefix used to distinguish packets coming from or going to the Intel explained in Section 3.3.1, “Ethernet Packet Formats Over the Backplane” on page By default, the driver works with the prefix enabled ...
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... The application has been modified to support backplane fabric ports and it uses IXB2850 firmware. Only the Linux version of the core components are supported for IXB2850 boards. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 24 Firmware/IXB28x0/Linux/drivers/ixd4gea1f/bin Section 2.4.3.2, “Starting Linux” on command to load the ixf1104drv_kernel ...
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... Document Number: 05-2443-006 file for details). 2801-POSEthIPv4Fwd-readme.pdf file to the application directory in the IXB2850 root file rtm_config_linux.sh file for details the IP address of the port where you ping Intel NetStructure 2801-POSEthIPv4Fwd- file for details). microcode (see the 2801- ® IXB2850 Packet Processing Boards ...
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... IXB2850—Hardware Overview Forwarding NP Media Access Module GE Mezzanine Card Adjunct Processor (Optional) Backplane Access Module 10Eth UARTs SPI-3 IXF1104 MAC Fabric Interface PCI Card, FIC (on IXB28504XGBEFSx boards) 4x GbEth (Cx) 12x GbEth (Cx) 4x (Cx) Crosspoint switch 8x GbEth (Cx) ATCA FABRIC CHANNEL I/F (1000BASE-CX) - port 1&2 ...
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... The baseboard contains two processors that include firmware: • Board Management Controller (BMC) - This processor is responsible for communication with Shelf Management Controllers (ShMCs) via the Intelligent Platform Management Bus (IPMB) on the backplane. It also manages power for the entire board and provides access to the ID EEPROMs located on the baseboard and all other cards ...
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... Mezzanine Card Fabric Interface Card (FIC) (IXB28504XGBEFSx boards only) The main component of the Media Access Module is the SPI-3/4 Bridge chip, which supports three peripheral SPI-3/UTOPIA buses. The SPI-3/4 Bridge chip is a bridge type device. It does not allow switching of traffic directly between peripheral buses; all traffic is bound to or from the network processor, and any switching between peripheral buses, if required, must be implemented in the network processor ...
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... Quad Gigabit SPI-3 Ethernet MAC Port 0 Port 1 Port 2 Port 3 3.3VCC 2.5VCC CPU Interface CPLD 4256V 3.3VCC JTAG from BB 4064 JTAG router SW 4x2 JTAG configuration Intel NetStructure Figure 9. PN13 4xSerDes PN15 PORT 0 PORT 1 PORT 2 PORT 3 Slow Port ® IXB2850 Packet Processing Boards TPS 29 ...
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... SPI-3 32bit Personality Mezzanine Card #2 SPI-3 32bit Fabric Interface Connection Paths Base Interface Connection Path in configuration without PrPMC Base Interface Connection Path in configuration with PrPMC ® Intel NetStructure IXB2850 Packet Processing Boards TPS 30 RTM ATCA FABRIC CHANNEL I/F (1000BASE-CX) (1000-Cx) Channel 1 ...
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... January 2007 Document Number: 05-2443-006 Figure 11. Prepended Header: 0x00000000 = Baseboard IXF1104 Packet 0x00000001 = FIC Packet (as shown) Reserved: Always 0x00000000 | 0x00 | 0x01 | In-band Addressing Header | 0x00 | 0x00 | | 0xaa | 0xbb | L2 Header | . Intel NetStructure insmod ® IXB2850 Packet Processing Boards TPS 31 ...
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... The interface to the network processor is supported through a SPI3 media interface, and the PHY interfaces are Serialized/Deserialized (SerDes) with GBIC support, Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII) selected on a per-port basis. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 32 FIC ...
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... Gigabit Ethernet MAC Port 0 Port 1 Port 2 Port 3 Q 125MHz LED_LINK10 Marvell* Alaska LED_LINK100 LED_LINK1000 Quad LED_DUPLEX LED_TX Gigabit Ethernet LED_RX PHY CONFIG[6:0] MAGNETIC MAGNETIC MAGNETIC Intel NetStructure EEPROM Board ID I2C Bus Temperature & Voltage sensor ® IXB2850 Packet Processing Boards TPS 33 ...
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... NP and other baseboard devices via the PCI bus (data traffic as well as configuration and management information). Note: IXB2850 boards can support only one PMC card at the time. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 34 IXB2850—Hardware Overview January 2007 ...
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... Shelf Management Controller (ShMC). Just after board power-on, the BMC establishes a connection with the ShMC over the Intelligent Platform Management Bus (IPMB) on the backplane. After providing the ShMC with information about the board hardware, the BMC enables power for the entire board on request from the ShMC ...
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... I C buses over the backplane) Connections to ID EEPROMs and sensors installed on the baseboard and extension cards Serial connection to the NP and CPU on extension cards and debug console IXB2850—Hardware Management FIC (IXB28504XGBEFSx only) QUAD UART UART A SEEPROM UART B TEMPERATURE UART C VOLTAGE ...
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... Hot Swap The IXB2850 board design provides a mechanism for implementing High Availability (HA) systems, supported by the Hot Swap and Intelligent Platform Management Interface (IPMI) control subsystem that integrates the following elements: • Hot Swap controller, Maxim* MAX5900 • Board Management Controller (BMC) • ...
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... If the -48 volt supply is operational, the MAX5900 hot-swap controller is started by the BMC power supply. • The BMC local system is started. • The blue LED is on. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 38 Section 4.4.2, “Board Insertion” on page 38 39. ...
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... The -48 volt early power supply, -48 volt ground, logic ground, and chassis ground are disconnected from the board. • Board removal is complete. 4.5 Board Reset The IXB2850 board reset circuit is shown in January 2007 Document Number: 05-2443-006 Figure 16. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 39 ...
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... The NPU can be reset for the following reasons: • Operator initiated NPU reset A software reset performed at the request of the operator from within the Boot Monitor, or from the operating system (for example, following a diagnostics or firmware upgrade). ® Intel NetStructure IXB2850 Packet Processing Boards TPS 40 NPU Reset NPU ...
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... BMC and uses BMC internal times. This watchdog has a configurable interval (up to 120 sec.) and can be enabled, disabled and kicked by the NPU using dedicated IPMI commands. Figure 17 January 2007 Document Number: 05-2443-006 shows the watchdog timers used by the NPU. Intel NetStructure ® IXB2850 Packet Processing Boards TPS 41 ...
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... Figure 17. Watchdog timers used by the NPU Disable BMC NPU watchdog RedBoot command line ® Intel NetStructure IXB2850 Packet Processing Boards TPS 42 Power Up Recovery Loader Enable 250 ms CPLD watchdog Start RedBoot Disable CPLD watchdog; enable BMC NPU watchdog for 120s Start boot ...
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... FRU information. The BMC has access to these ID EEPROM devices over the bus. The BMC supports the following hardware modules: • IXB2850 baseboard ® • Intel IXP2850 network processor module • Quad Gigabit Ethernet Mezzanine Card January 2007 Document Number: 05-2443-006 90. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 43 ...
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... FRU. The “Not supported (C1h)” code is returned for this command issued for other FRUs. Consult the IPMI v1.5 and the PICMG v3.0 specifications for more information on “mandatory” and “optional” commands. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 44 Table 5, with the exception of the baseboard FRU (ID=00h), IXB2850— ...
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... Record x Optional – A description of backplane interfaces – Ethernet interface MAC address definition – A sensor device description – A memory amount definition - BMP and NPU boot parameters Section 8.4.2, “Point-to-Point Connectivity Records” on ® Intel NetStructure IXB2850 Packet Processing Boards TPS 45 ...
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... Manufacturer ID. LS byte first. Write as a three byte ID = 000157h. Record Format Version/Intel Record ID: • 7:5 – MAC Addresses Record format version (=0h for this definition) • 4:0 – Intel Record ID. For the MAC Addresses Record, a value 00h should be used. MAC Address Definition list. A variable-length list of eight-byte MAC Address Definitions (see Table 8) totaling m bytes in length ...
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... Manufacturer ID. LS byte first. Write as the three byte ID = 000157h. Record Format Version/Intel Record ID: • 7:5 – Sensor Devices Record format version (=0h for this definition) • 4:0 – Intel Record ID. For the Sensor Devices Record, a value 01h should be used. Sensor Descriptor list. A variable length list of six-byte Sensor Descriptors (see Table 10) totaling m bytes in length ...
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... Manufacturer ID. LS byte first. Write as the three byte ID = 000157h. Record Format Version/Intel Record ID: • 7:5 – Memory Amount Record version (=0h for this definition) • 4:0 – Intel Record ID. For the Memory Amount Record, a value 02h should be used. Memory Definition list. A variable-length list of five-byte Memory Definitions (see Table 12) totaling m bytes in length ...
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... Manufacturer ID. LS byte first. Write as the three byte ID = 000157h. Record Format Version/Intel Record ID: • 7:5 – Processors Boot Parameters Record version (=0h for this definition) • 4:0 – Intel Record ID. For the Processors Boot Parameters Record, a value 03h should be used Processor Descriptor list. A variable-length list of variable-length Processor ...
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... Offset Length (bytes) (bytes ® Intel NetStructure IXB2850 Packet Processing Boards TPS 50 Definition Boot flags: • 7:5 – BMC Boot Parameters definition format version (=0h for this definition) • 4:4 – POST type. A flag indicating type of Power-On-Self-Test (POST) performed by BMC during board startup. This parameter can have one of two values: ...
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... Image Loading Parameters Set list. A variable-length list of variable-length Image Loading Parameters Sets (see Table 17) totaling m bytes in length. Each Image Loading Parameter Set describes parameters necessary to download and run one run- time image. Intel NetStructure ® IXB2850 Packet Processing Boards TPS 51 ...
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... Length (bytes) (bytes ® Intel NetStructure IXB2850 Packet Processing Boards TPS 52 Definition Loading Parameters Set flags: • 7:7 – End of List. Set to one for the last record. • 6:4 – Set Type – Image Loading Parameters Set type. For flash loading parameters a value 0h shall be used. • ...
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... Board Info Area PICMG Point-to-Point Connectivity Record for base interface and fabric interface channel 1 MAC Address Records for the Dual Port Gigabit Ethernet Controller (Intel SPI-3 Gigabit Ethernet MAC Controller (Intel Ethernet (CS8900) Sensor Device Records for all sensor devices on the baseboard ...
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... Device node – The number of a physical sensor within the confines of the referenced physical multi-sensor device. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 54 Section 8.6, “Non-Volatile Storage Programming” on page ...
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... Sensor device FRU OEM record Device ID Device type Device address (8 bits) (8 bits) (32 bits) BMC sensor map entry Device type Device address Bus number (8 bits) (32 bits) (8 bits) following). ® Intel NetStructure Figure 19 Device node (8 bits bus) IXB2850 Packet Processing Boards TPS 55 ...
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... Sensor Number 9 Entity ID 10 Entity Instance 11 Sensor Initialization 12 Sensor Capabilities ® Intel NetStructure IXB2850 Packet Processing Boards TPS 56 Table 21 lists sensor types supported by IXB2850 boards. SDR Type Full Sensor Record (SDR Type 01h) Full Sensor Record (SDR Type 01h) Full Sensor Record ...
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... OEM information • 7:5 – reserved • 4:1 – Processor ID: - 00h BMC - 01h NPU#1 - 02h NPU#2 - 03h PrPMC (for example, an Adjunct Processor) • 0:0 – Virtual Console Not supported - 1b Supported ® Intel NetStructure IXB2850 Packet Processing Boards TPS 57 ...
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... IXB2850 board operation. When the BMC detects that a particular sensor reading exceeds one of the thresholds defined in the SDR record, it sends an appropriate event to ShMC. The ShMC is responsible for responding to these events appropriately (for example, powering a board off). ® Intel NetStructure IXB2850 Packet Processing Boards TPS 58 Table 23 ...
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... Mezzanine Card). It can control these LEDs indirectly via the BMC Agent running on the NPU. To force all application-specific LEDs on or off during the lamp test operation, the BMC must send an IPMI command to BMC Agent, which is responsible for LED control. January 2007 Document Number: 05-2443-006 37. Intel NetStructure Section ® IXB2850 Packet Processing Boards TPS 59 ...
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... Controls, Indicators and Connectors 5.1 Front Panels Figure 20 shows the controls, indicators and connectors on the front panel of Intel ® NetStructure IXB28504XGBEFSx boards. Figure 20. IXB28504XGBEFSx board front panel COM ETH 10M Port Port Status LEDs OOS HEALTH LED LED The function of each component is described in the following subsections. ...
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... Gigabit Ethernet Ports For IXB28504XGBEFSx boards, the Quad Gigabit Ethernet Mezzanine Card operates in conjunction with a Fiber Media Interface Card (MIC-F) to provide four 1000BASE-SX fiber ports with status LEDs to the front panel. ...
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... ZD high-speed connectors. • Zone 3: RTM (Not Used) R30 connector; rear panel I/O; not used on the IXB2850 boards. Figure 21 shows the locations of the backplane connectors. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 62 IXB2850—Controls, Indicators and Connectors January 2007 Document Number: 05-2443-006 ...
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... Backplane Top Edge J20 Telephony Clock Interface Update Port Interface J21 J22 Fabric Interface J23 Base Interface J24 Note: J24 connector is not mounted P10 Power Distribution and System Management Power Connector Positronic Industries* Intel NetStructure Table 24 provides ® IXB2850 Packet Processing Boards TPS 63 ...
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... HA0 Hardware Address Bit 7 (odd parity bit) 13 SCL A IPMB Clock, Port A 14 SDA A IPMB Data, Port A 15 SCL B IPMB Clock, Port B 16 SDA B IPMB Data, Port B 17 Spare 18 Spare 19 Spare ® Intel NetStructure IXB2850 Packet Processing Boards TPS 64 IXB2850—Controls, Indicators and Connectors ...
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... This is an ERNI/Tyco/AMP connector. Its plug (located on the baseboard) has part number 1469001-1. January 2007 Document Number: 05-2443-006 Mating Sequence On Insertion N/A N/A N/A N/A N/A First First Fifth First First First First Fifth Second Third Figure 23 shows a single ZD ® Intel NetStructure IXB2850 Packet Processing Boards TPS 65 ...
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... ZD pairs on the ZD connector. Figure 24. Zone 2 data transport connector base channel and fabric channel port allocation ZD Connector ® Intel NetStructure IXB2850 Packet Processing Boards TPS 66 IXB2850—Controls, Indicators and Connectors Single Base Channel Single Fabric Channel Four 2-pairs ports 1000BASE-BX Port 2 Port ...
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... Channel 6 Base Channel Interface Channel 7 Channel 8 Channel not used Channel 9 Note: J24 is not installed. Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Intel NetStructure and Table 26 give the pin Figure 25). Fabric Channel Interface (occupy 4x 4-pairs) 2x 1000BASE-T ports (occupy 2x 4-pairs) ® IXB2850 Packet Processing Boards ...
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... Pin Assignment Format: Tx/Rx I[J]K where transmit receive differential pair number ( channel designator (1 to 15) and K = polarity (+ or -). 5.2.3 Zone 3: RTM (Not Used) A Rear Transition Module (RTM) connector. Not used on IXB2850 boards. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 68 IXB2850—Controls, Indicators and Connectors C D ...
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... PN9, and PN10) are required to provide a 192-pin connection between the two boards (64-bit PCI Bus). The PN11 connector is used for user-defined I/O signals. January 2007 Document Number: 05-2443-006 PN1 PN8 PN9 PN10 PN11 Intel NetStructure ® IXB2850 Packet Processing Boards TPS 69 ...
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... DEVSEL# 39 GND 41 PCI-RSVD 43 PAR 45 V(I/O)3.3V 47 AD[12] 49 AD[09] 51 GND 53 AD[06] 55 AD[04] 57 V(I/O) 59 AD[02] 61 AD[00] 62 GND ® Intel NetStructure IXB2850 Packet Processing Boards TPS 70 IXB2850—Controls, Indicators and Connectors Remarks Pin# Description JTAG 2 -12V 4 INTA# 6 INTC# 8 +5V 10 PCI-RSVD 12 3.3Vaux 14 GND 16 GNT# 18 +5V 20 AD[31] ...
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... GND 8 PCI-RSVD 10 PCI-RSVD 12 3.3V 14 PDN1 16 PDN2BUSMODE#4 18 GND 20 AD[29] 22 AD[26] 24 3.3V 26 AD[23] 28 AD[20] 30 GND 32 PCI_CBE#2 34 IDSELB 36 3.3V 38 STOP# 40 GND 42 SERR# 44 GND 46 AD[13] 48 AD[10] 50 3.3V 52 PCI_RSVD 54 PCI-RSVD 56 GND 58 EREADY 60 RESETOUT# 62 3.3V 64 MONARCH# ® Intel NetStructure Remarks JTAG JTAG IXB2850 Packet Processing Boards TPS 71 ...
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... AD[45 (I/O) 41 AD[43] 43 AD[41] 45 GND 47 AD[39] 49 AD[37] 51 GND 53 AD[35] 55 AD[33 (I/O) 59 PCI-RSVD 61 PCI-RSVD 62 GND ® Intel NetStructure IXB2850 Packet Processing Boards TPS 72 IXB2850—Controls, Indicators and Connectors Remarks Pin# Description 2 GND 4 C/BE[7] 6 C/BE[5]# 8 GND 10 PAR64 12 AD[62] 14 GND 16 AD[60] 18 AD[58] 20 GND 22 AD[56] ...
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... PMC_CHA_MDI3+ 1000BASE-T – port 0 10 PMC_CHA_MDI3+ 12 GND 14 PMC_CHB_MDI2+ 1000BASE-T – port 1 16 PMC_CHB_MDI2+ 18 GND 20 PMC_CHA_MDI3+ 1000BASE-T – port 1 22 PMC_CHA_MDI3+ 24 GND SCL_I2C_FIC_LOCAL PMC I 34 SDA_I2C_FIC_LOCAL PCM TXD UART 44 RTS UART +3.3V (early power) 64 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 73 ...
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... Two redundant Shelf Management Controllers (ShMCs) • Two redundant Switch Fabrics boards • Backplane, which includes the following interfaces within the confines of a slot designed for an IXB2850 board: — Intelligent Platform Management Bus (IPMB dual I C bus connecting the ShMCs with each board in the chassis. ...
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... SW2 S1 J7 J38 (on IXB28504XGBEFSx Fabric Interface Connector Slot for Adjunct Processor PCI Mezzanine Card (PMC) J2 Note: IXB28504XGBEFSx boards use a mezzanine card with fiber interfaces as shown. Intel NetStructure Fabric Interface Card, FIC Boards) Base and Connectors Power ® IXB2850 Packet Processing Boards ...
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... OFF — — — — • SW2: Default settings are: — 1: OFF — 2: OFF — — 4: OFF — 5: OFF — 6: OFF — — ® Intel NetStructure IXB2850 Packet Processing Boards TPS 76 IXB2850—Installation and Configuration January 2007 Document Number: 05-2443-006 ...
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... If you are installing a shelf manager in your AdvancedTCA chassis, J2 pins 1-2 must be set ON. If you are not installing a shelf manager, J2 pins 1-2 must be set OFF. January 2007 Document Number: 05-2443-006 for details. Default settings are: ® Intel NetStructure IXB2850 Packet Processing Boards TPS 77 ...
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... Remove the board from the chassis as follows: 1. Loosen both of the board’s front panel retaining screws. Caution: Do not remove the board until the H/S indicator is lit continuously (that is, not flashing). ® Intel NetStructure IXB2850 Packet Processing Boards TPS 78 IXB2850—Installation and Configuration January 2007 ...
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... Boot Section 8.1.2.1, “BMC Power On Self Test” on page 86 image does not contain an SSU header invalid. diag command output (step 1 above). fis list Intel NetStructure for more information. for more information. ® IXB2850 Packet Processing Boards TPS ...
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... Intel NetStructure IXB2850 Packet Processing Boards TPS 80 IXB2850—Installation and Configuration Description Print a hardware/software information banner. Copy a memory block. Change the contents of a memory address. Read/write data from/to a PCI device. Disable data cache. ...
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... Perform MSF tests. Perform PCI tests. Perform slow port tests. Perform UART tests. Perform a microengine test. ® Perform Intel XScale scratchpad and core component tests. Write, read and verify content in a specified memory address. Intel NetStructure ® IXB2850 Packet Processing Boards ...
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... When power is switched on, the BMC releases an NPU reset signal. The NPU starts execution of the Initial Loader code and controls the reset signals for all other components on the board. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 82 BMC local flash ...
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... NPU Boot Monitor Get HW Configuration Get reset reason Release AP reset after PCI initialization NPU run-time image Load and execute · Diagnostics NPU run-time image · Linux kernel Intel NetStructure AP AP BootROM or BIOS Start AP run-time image AP run-time image ® IXB2850 Packet Processing Boards ...
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... Linux* Support Package (LSP) The NPU firmware resides in onboard flash memory. See Processor Firmware” memory. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 84 for details on the organization and content of the for details on the organization and content of the NPU local flash IXB2850— ...
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... January 2007 Document Number: 05-2443-006 Figure 30. The content of the various BMC initial loader BMC operational image #1 Image #1 descriptor BMC operational image #2 Image #2 descriptor System Events Log Temporary upgrade storage Intel NetStructure ® IXB2850 Packet Processing Boards TPS 85 ...
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... Keyboard Controller Style (KCS) • LEDs • Timers Interrupt (IRQ) POST Interrupt controller verification testing is available, including simulated interrupts. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 86 IXB2850—Board Management Controller Firmware describes BMC dual image Section 11.5, “Remote BMC Firmware Upgrade” ...
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... The following tests are executed using the UARTs in loopback mode: • Register access • Non-FIFO polling • Non-FIFO interrupt • FIFO polling • FIFO interrupt January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 87 ...
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... The BMC stores the following events in the event log: • All IPMI events generated by the BMC • All IMPI events generated by the NPU (or AP) and forwarded by the BMC • All reset events (entire board, NPU, or BMC) ® Intel NetStructure IXB2850 Packet Processing Boards TPS 88 IXB2850—Board Management Controller Firmware 32 ...
Page 89
... Event Access commands and must not be used as the Record ID values for stored SEL Event Records. Record Type = OEM System Event Record (C0h) Time when event was logged; LS byte first Manufacturer ID = 5A3100h Event Type = Reset (00h) Intel NetStructure Table 33 (compare Table 34 (compare to ® ...
Page 90
... The BMC also supports the PICMG 3.0 OEM mandatory command set. See 8.2.2, “PICMG 3.0 IPMI Command Support” on page 95 support. In addition, the BMC supports a set of Intel OEM commands and board-specific commands. See Appendix D, “OEM IPMI Commands” 8.2.1 IPMI 1 ...
Page 91
... Additional constraints apply; S/E 21h M S see the IPMI 1.5 specification Additional constraints apply; S/E 22h M S see the IPMI 1.5 specification Additional constraints apply; S/E 23h O N see the IPMI 1.5 specification ® Intel NetStructure IXB2850 Packet Processing Boards TPS 91 ...
Page 92
... Get BMC Global Enables Clear Message Flags Get Message Flags Enable Message Channel Receive M/O identifies if a command is Mandatory or Optional S/N identifies if a command is Supported or Not supported by the BMC ® Intel NetStructure IXB2850 Packet Processing Boards TPS 92 IXB2850—Board Management Controller Firmware S/ NetFn ...
Page 93
... Additional constraints apply; App 47h O N see the IPMI 1.5 specification Additional constraints apply; App 52h O/M S see the IPMI 1.5 specification Storage 10h M S Storage 11h M S Storage 12h M S Storage 20h M S ® Intel NetStructure IXB2850 Packet Processing Boards TPS 93 ...
Page 94
... Get SEL Time Set SEL Time Get Auxiliary Log Status Set Auxiliary Log Status M/O identifies if a command is Mandatory or Optional S/N identifies if a command is Supported or Not supported by the BMC ® Intel NetStructure IXB2850 Packet Processing Boards TPS 94 IXB2850—Board Management Controller Firmware S/ NetFn ...
Page 95
... Command required by the BMC controlling Shelf 15h O/M N fans Command required by the BMC controlling Shelf 16h O/M N fans Mandatory for boards implementing E-Keying- 17h O/M S governed shared bus interfaces 18h O/M N Mandatory for BMC incorporating an IPMB-0 Hub ® Intel NetStructure IXB2850 Packet Processing Boards TPS 95 ...
Page 96
... Responder’s Slave Address for remote message Data 5 Requester’s Sequence Number and Responder’s LUN for the remote message Data 6 Command for the remote message ® Intel NetStructure IXB2850 Packet Processing Boards TPS 96 IXB2850—Board Management Controller Firmware Document Number: 05-2443-006 ...
Page 97
... Document Number: 05-2443-006 Description Completion Code for the remote message Data for the remote message Checksum 2 for the remote message Checksum 2 for the Send Message command Intel NetStructure describes in detail all the describes all IPMI ® IXB2850 Packet Processing Boards TPS ...
Page 98
... BMC and receive a response. In this phase, only the NPU can start message exchange between the NPU and BMC. diagram illustrating the cooperation between the NPU and BMC in this phase. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 98 IXB2850— ...
Page 99
... NPU E-Keying Boot Backplane Status Word Monitor Driver Get Port State Setup port(s) Set Port State Interrupt Setup port( UML diagram illustrating cooperation between the NPU Intel NetStructure Operations initiated by Boot Monitor Operations initiated by ShMC ® IXB2850 Packet Processing Boards TPS 99 ...
Page 100
... Port Port Port Port Port Port Port 2 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 100 IXB2850—Board Management Controller Firmware E-Keying NPU Status Word BMC Agent Get Port State Read Status Word Setup port(s) Update Status Word Set Port State ...
Page 101
... Record Format Version 0 OEM GUID Count Link Descriptor list. See: • Table 41, “Link descriptors for fabric interface channel 1” on page 102 • Table 42, “Link descriptors for base interface channels” on page Intel NetStructure 102. ® IXB2850 Packet Processing Boards TPS 101 ...
Page 102
... Intel NetStructure IXB2850 Packet Processing Boards TPS 102 IXB2850—Board Management Controller Firmware Value Description 111101000001b Channel Number = 1; Interface = Fabric; Port 0,1,2,3 Enabled 02h Link Type = PICMG 3.1 Ethernet 0000b Link Type Extension = 1000BASE-BX 00h Link Grouping ID = Independent Value Description 000100000001b Channel Number = 1 ...
Page 103
... Link Type = PICMG 3.1 Ethernet 0000b Link Type Extension = 1000BASE-BX 00h Link Grouping ID = Independent Section 12.8.1, “Debug Console Cable for details). In single mode, this connector works like a following for more details. Intel NetStructure ® IXB2850 Packet Processing Boards TPS 103 ...
Page 104
... PMC SDR Information The BMC can update the content of all these areas using the IPMI protocol. The UML diagram in Figure 33 storage programming. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 104 IXB2850—Board Management Controller Firmware Non-volatile storage BB ID EEPROM MMC1 ID EEPROM; not applicable to IXB2850 boards MMC2 ID EEPROM MIC1 ID EEPROM ...
Page 105
... Set Segment (NetFn=08h/09h; CMD=05h) Completion Code Download(NetFn=08h/09h; CMD=01h) Completion Code Download(NetFn=08h/09h; CMD=01h) Completion Code Burn Image (NetFn=08h/09h; CMD=0Ch) Completion Code Completion Code Exit Xfer Mode(NetFn=08h/09h; CMD=04h) Completion Code Figure 33 Intel NetStructure BMC to upgrade non-volatile storage ® IXB2850 Packet Processing Boards TPS 105 ...
Page 106
... All 16/32-bit values are stored in the system native Endian type; all fields with variable length are stored using a strings-like method (byte after byte) starting from the lowest address. The NPU local flash memory layout is shown in ® Intel NetStructure IXB2850 Packet Processing Boards TPS 106 Image ...
Page 107
... A local data storage for Boot Monitor and Diagnostics. Handles all necessary information that is used during system start, for example, IP address configuration (static IP configuration or configuration using BOOTP requests) and run-time image loading script. Contains information on all flash entries. Intel NetStructure Table 47 for ® IXB2850 Packet Processing Boards ...
Page 108
... Run-time image loading Ethernet BOOTP request number SRAM initialization Script timeout Ethernet tracing Debug Ethernet IP configuration type ® Intel NetStructure IXB2850 Packet Processing Boards TPS 108 IXB2850—Network Processor Firmware Table 48 for details. Purpose Contains a Linux kernel image. Contains a Linux root file system. ...
Page 109
... Base Interface #2 † IP configuration Run-time image searching sequence † By default, RedBoot* routes the Intel and the baseboard PHYs to base interfaces. See The Boot Configuration parameters can be changed using dedicated Boot Monitor commands. The BMC and ShMC are also able to change these parameters via a dedicated OEM FRU record ...
Page 110
... The Boot Manager can use such an interface for TFTP code downloading. — Gigabit Ethernet controller driver – a driver for the Intel 82546 Dual Port Gigabit Ethernet Controller connected to the NPU via the PCI bus. This controller enables the NPU to access the AdvancedTCA base interface ...
Page 111
... Information record and modifies the Boot Monitor Config Status Word to run the new Boot Monitor Configuration in “safe mode” (see Section January 2007 Document Number: 05-2443-006 128). Section 4.6.2.5, “Processors Boot Parameters Record” on Section 11.2.2.2, “Image Intel NetStructure for details). This ® IXB2850 Packet Processing Boards TPS 111 ...
Page 112
... Boot Monitor Config upgrade procedure is postponed until the next NPU startup. 9.4.3 NPU Power On Self Test The Power-On Self Test (POST) performs initialization and basic tests on the Intel ® XScale core and the main baseboard components that the XScale core depends on. ...
Page 113
... C • LEDs • Mezzanine with Gigabit Ethernet • FIC (IXB28504XGBEFSx boards only) • Telecom clock test The POST results are displayed on the console and saved in the System Events Log (SEL). After the boot process is finished, the results can be retrieved and used by an operating system ...
Page 114
... Definition of configuration – The user can change the Boot Configuration parameters stored in a dedicated sector of flash memory. A detailed specification of the console commands can be found in the RedBoot User Guide (see http://sources.redhat.com/ecos/docs-latest/redboot/redboot-guide.html). ® Intel NetStructure IXB2850 Packet Processing Boards TPS 114 IXB2850—Network Processor Firmware ...
Page 115
... Indicates that the Event Data 3 field contains an OEM code Offset from the Event/Reading Type Code from the SDR describing a given CPU sensor. This offset has the meaning of the event class. For details, see format” on page 56. Intel NetStructure 50. Table 51. The Table 22, “Processor SDR ® ...
Page 116
... PCI Ethernet 08h – ME#0 to 17h – ME#15 18h – Slow port 19h – Interrupts 1Ah – XScale core 1Bh – MSF 1Ch – GPIO ® Intel NetStructure IXB2850 Packet Processing Boards TPS 116 Table 52 Data 3 (Event Additional Description Information) Reset type: • ...
Page 117
... Access – mode 1 23h – MMC#2 Media Access – mode 1 25h – Baseboard Media Traffic 26h – FIC Media Traffic (IXB28504XGBEFS boards only) 27h – MMC#1 Media Traffic – mode 1 29h – MMC#2 Media Traffic – mode 1 2Bh – Telecom Clocks ...
Page 118
... Media Access – mode 1 23h – MMC#2 Media Access – mode 1 25h – Baseboard Media Traffic 26h – FIC Media Traffic (IXB28504XGBEFSx boards only) 27h – MMC#1 Media Traffic – mode 1 29h – MMC#2 Media Traffic – mode 1 2Bh – Telecom Clocks ® ...
Page 119
... Slow port Ethernet tests • PCI Ethernet tests • MSF tests • Microengine tests • Media tests • FIC tests (IXB28504XGBEFSx boards only) • Telecom Clock tests Every diagnostic test error is reported to the ShMC via an IPMI event message sent to the BMC as described in See Appendix C, “ ...
Page 120
... The LSP kernel provides support for interrupt sources specific to: • IXP2850 network processor • IXB2850 baseboard The IXP2850 network processor interrupts are described in detail in Intel IXP2800 Network Processor Programmer’s Reference Manual. IXB2850 baseboard interrupts are managed through a set of internal CPLD registers accessible through the NP slow port ...
Page 121
... On-board Marvell* Alaska 1011 Gigabit Ethernet PHY • On-board CS8900A 10 Mb Ethernet controller • On-board 16C550 UART controller • Fabric Interface Card (FIC, IXB28504XGBEFSx boards only) • Gigabit Ethernet Mezzanine Card in slot DB#2 The board reset procedure takes care of switching to bank 0 of the flash memory during system reset (see 9 ...
Page 122
... MB slow port window divided into 5 banks, each comprising two 16 MB chips. The LSP kernel contains an MTD map driver modified to support appropriate bank switching. Figure 37 shows the concept of flash memory bank switching. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 122 IXB2850—Network Processor Firmware Figure ...
Page 123
... The I/O functions of a Linux standard Ethernet driver have been modified to: • Remove PC/ISA-related dependencies • Support 32-bit access (hardware requirement) • Provide a workaround for microengine performance throttling during on-board port activity January 2007 Document Number: 05-2443-006 16 MB Flash 5 banks * Flash ® Intel NetStructure IXB2850 Packet Processing Boards TPS 123 ...
Page 124
... Sending IPMI event messages to ShMC The BMC Access interfaces are shown in Figure 38. BMC Access interfaces BMC Agent ATM/POS GE driver driver ® Intel NetStructure IXB2850 Packet Processing Boards TPS 124 and the RedBoot User’s Guide (see Section 8.3.1, “Serial Connections” on page 97 Figure 38. Safe System ...
Page 125
... Pointer to callback function invoked after a message is received Data decapsulated from the received IPMI message, that is, the message without the header information. Length of payload Description operation completed successfully operation error resource already registered by other process Intel NetStructure ® IXB2850 Packet Processing Boards TPS 125 ...
Page 126
... IN netFn IN cmd IN rqLUN Returns Return Code CC_OK CC_ERROR ® Intel NetStructure IXB2850 Packet Processing Boards TPS 126 IXB2850—Network Processor Firmware Description IPMI net function IPMI command Responder’s IPMI Logical unit number Description operation completed successfully operation error Description payload length in bytes pointer to message’ ...
Page 127
... IXB2850 board firmware: • Boot Monitor • Linux kernel • Linux root file system • Linux target application • BMC firmware January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 127 ...
Page 128
... EEPROM before the driver starts. 9.7.1 Configuration Settings The Baseboard driver initialization parameters in initialization. For Linux systems, this is done in the command line with insmod. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 128 IXB2850—Network Processor Firmware Table 55 must be set up during driver ...
Page 129
... Packet Formats Over the Backplane” on • 1 page 31. By default, the use of the 64- Default = 0 bit prefix is enabled. Specifying noFabricPrepend=1 disables the use of the prefix. Intel NetStructure for elements that are Valid Values dev0=spi3:odd dev1=spi3:odd dev2=spi3:odd noFabricPrepend=1 ® IXB2850 Packet Processing Boards ...
Page 130
... Using IXB2850 Boards with the IXA SDK 10.1 Introduction IXB2850 boards can be used with the Intel® Internet Exchange Architecture Software Development Kit (Intel® IXA SDK) to enable application development and in-depth testing to validate data paths, device functionality, system functionality, device driver behavior and the Linux Support Package (LSP) software. For more information about the IXA SDK, see the Intel® ...
Page 131
... Note that all images can be upgraded at once or the upgrade process may be performed for the selected image. The SSU module includes two main elements (see • SSU Agent (SSUA) January 2007 Document Number: 05-2443-006 Section 11.4.1, “Safe System 152). Figure 39): ® Intel NetStructure IXB2850 Packet Processing Boards TPS 131 ...
Page 132
... In order to support the automatic rollback mechanism in case of image upgrade failure (invalid image, part of image hangs, kernel fatal error during initialization, target image does not work properly, etc.), a dual image concept must be supported. The concept is based on the following assumptions: ® Intel NetStructure IXB2850 Packet Processing Boards TPS 132 SSU Manager ...
Page 133
... This bit selects the active image to be loaded (either the first or the second copy). This bit may be modified only by the SSUA on a control plane validation request. Unused Intel NetStructure Figure 40 0 ® IXB2850 Packet Processing Boards TPS ...
Page 134
... Board Reboot Initial Loader detected board reboot without SSUM validation Upgraded image was invalid ® Intel NetStructure IXB2850 Packet Processing Boards TPS 134 Description This bit is set by the SSUA to force the Boot Monitor to use the second copy of the configuration script in safe mode. ...
Page 135
... Document Number: 05-2443-006 to unused partition configuration record startup script from BootMonitorConfig1 partition Board Reset (watchdog, management) application Restart previous BootMonitor Version, BootMonitor config script, clear Boot Mode indicator bits Intel NetStructure Boot Boot Monitor Monitor SW config SW 000xxxxx 000xxxxx 000xxxxx 000xxxxx 100xxxxx 100xxxxx ...
Page 136
... It is possible to read from the SSUM the attributes of each image stored in flash. The SSUA reads this information from the image header that has been verified and added after the image update possible to retrieve an image header for one image or a group of images. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 136 IXB2850—Maintenance ...
Page 137
... January 2007 Document Number: 05-2443-006 Table 58 and Table 59 ® Intel NetStructure IXB2850 Packet Processing Boards show TPS 137 ...
Page 138
... Use the cfg read boot monitor console command to check hardware versions. 1 “Earlier generation boards” include IXB28504XGBEFS boards, which may contain restricted substances. 2 Shown here for completeness only; upgrade not always required; check the software Release Notes for a list of components to upgrade. ...
Page 139
... IXB28504XGBEFSW and IXB28504XGBEFSR, which are lead-free to second level interconnect. 2 Shown here for completeness only; upgrade not always required; check the software Release Notes for a list of components to upgrade. ...
Page 140
... Validate the new RedBoot image: RedBoot> ssu validate -i Image "RedBoot" of type <<bootmonitor>> passed SSU validation ! 5. Repeat steps upgrade the second image. In the event of failure, see Problems” on page 141 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 140 bootmonitor Section 11.3.1.1.1, “Troubleshooting RedBoot Upgrade following. ...
Page 141
... Download the appimage loader with the command: RedBoot> load - TFTP -b 0x3000000 /tftpdir/<release_version>/ appimage_loader.bin - Raw file loaded 0x03000000-0x0303810c 2. Execute the loader: RedBoot> go January 2007 Document Number: 05-2443-006 file (available in the firmware package in the . prompt, type . fis image Intel NetStructure directory) to ® IXB2850 Packet Processing Boards TPS 141 ...
Page 142
... RedBoot> ssu upgrade -b 0x03000000 -l 0x40000 - .BMC image updated. Note: This operation takes approximately 10 minutes. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 142 at 0xc4000000..0xc401ffff from 0x0001cebc - are you sure (y/n)? y fis delete command) prior to issuing the IXB2850—Maintenance fis create command ...
Page 143
... DAMAGE. Are you sure (Y/N)? BMC Service 2 menu: 1: load image using xmodem 2: Burn-in BOOT part of flash with loaded data 0: Exit this menu January 2007 Document Number: 05-2443-006 , connect to the BMC minicom ® Intel NetStructure IXB2850 Packet Processing Boards TPS 143 ...
Page 144
... BMC Loader version 2.06 ------------------------------ 11.3.1.6 Upgrading FRU Information and SDRs The following subsections provide information about upgrading FRU information and Sensor Device Records (SDRs). ® Intel NetStructure IXB2850 Packet Processing Boards TPS 144 IXB2850—Maintenance January 2007 Document Number: 05-2443-006 ...
Page 145
... FRU update ended. TURN OFF AND ON POWER January 2007 Document Number: 05-2443-006 command. 139. Interface MAC Number Address 0 00:00:00:00:00:00 1 00:00:00:00:00:01 0 00:00:00:00:03:00 1 00:00:00:00:03:01 0 00:00:00:00:06:00 1 00:00:00:00:06:01 2 00:00:00:00:06:02 3 00:00:00:00:06:03 Intel NetStructure update Table 58, “Components or Table 59, “Components -b 0x1000000 /tftpdir/ ® IXB2850 Packet Processing Boards TPS 145 ...
Page 146
... IXB2850 boards contains several in-system programmable Complex Programmable Logic Devices (CPLDs): • Baseboard NPU CPLD • Baseboard BMC CPLD • Baseboard JTAG router CPLD • NPU module CPLD ® Intel NetStructure IXB2850 Packet Processing Boards TPS 146 138. -b 0x1000000 /tftpdir/ Table 58, “Components to be upgraded for or Table 59, “ ...
Page 147
... FIC are similar and therefore not repeated here. 11.3.2 Local Software Upgrade of All Images at One Time Software upgrade may be performed using the IXP28x0_upgrade.bin appimage that contains all upgradeable images. January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 147 ...
Page 148
... Other FLASH images: diag_ixdp2801_ssu.bin FRU binaries: ixmb2801_3a_fru.bin ixmb2801_4_fru.bin ixmb2801_4_rohs5_fru.bin ixmb2801_3a_nofic_fru.bin ixmb2801_4_nofic_fru.bin ® Intel NetStructure IXB2850 Packet Processing Boards TPS 148 Section 11.3.2.1 for bb (Main board FRU, spin 3A with FIC) for bb (Main board FRU, spin 4 with FIC) for bb (Main board FRU, spin 4 with FIC (RoHS 5/6)) ...
Page 149
... SDR, 4-port fiber, spin 1, v2) for mic1 mic2 (MIC SDR, 4-port fiber, spin 2 (RoHS 6/6)) for fic (FIC SDR) for fic (FIC SDR (RoHS 5/6)) Section 11.3.2.2, “fis manifest” on ® Intel NetStructure IXB2850 Packet Processing Boards TPS 149 ...
Page 150
... The only recognized option is: • Identifies the image to be burned in flash. Possible images are: — redboot - Redboot* boot monitor — linux - Linux — rootfs - Linux root file system ® Intel NetStructure IXB2850 Packet Processing Boards TPS 150 IXB2850—Maintenance Section 11.3.2.2, “fis manifest” on 148) ...
Page 151
... Mark the newly downloaded image for one-shot test mode. 4. Reboot the board. 5. Verify that the new image has booted correctly and validate the new image. January 2007 Document Number: 05-2443-006 shows a typical image upgrade procedure: Intel NetStructure ® IXB2850 Packet Processing Boards TPS 151 ...
Page 152
... SSU Image Upgrade • SSU Change Image State (One-Shot) • SSU Validate All Images • SSU Upgrade Operation Status Command ® Intel NetStructure IXB2850 Packet Processing Boards TPS 152 SSU Manager NPU SSU Agent (Control Plane) SSU Image Get Information Image Information Array ...
Page 153
... Image description length 5+N:M Image description Value Description 0 Flash backup partition 1 Flash active partition Value Description 0 NPU Boot Monitor 1 NPU Linux kernel 2 NPU Root File System 3 NPU Target application image 4 BMC firmware Intel NetStructure ® IXB2850 Packet Processing Boards TPS 153 ...
Page 154
... Table 62. SSU image state State SSU_EMPTY SSU_INACTIVE SSU_ONESHOT SSU_ONESHOT_RUNNING SSU_ACTIVE ® Intel NetStructure IXB2850 Packet Processing Boards TPS 154 Valu Description e No image (flash partition empty). Initial state of the flash partition if no image is downloaded. The partition also enters this state when the image download fails because of a CRC error ...
Page 155
... TFTP 6:3 IP version 4 address of image repository server 7 Length of path string 8:N Path in remote repository 1 Completion Code (see below) Value Description 20h Upgrade operation failed Intel NetStructure 154). If there is no such partition, the ® IXB2850 Packet Processing Boards TPS 155 ...
Page 156
... SSU Image Upgrade Completion Code (In progress) SSU Upgrade Operation Status Completion Code (In progress) SSU Upgrade Operation Status Completion Code (Passed) ® Intel NetStructure IXB2850 Packet Processing Boards TPS 156 Value Description Upgrade operation is in progress. The final status of this operation should be obtained using SSU Upgrade Operation ...
Page 157
... Invalid Command (out of supported range) CCh Invalid Image Type Byte Data Field 1 Completion Code (see below) Value Description 00h Operation completed successfully C0h Responder busy (SSU Image Upgrade operation in progress) Intel NetStructure Table 62, “SSU image ® IXB2850 Packet Processing Boards TPS 157 ...
Page 158
... Reserved for future use After storing the new image, the BMC sends the status of the upgrade operation to the SSUA on the NPU, and the SSUA passes this status to the SSUM. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 158 Byte Data Field ...
Page 159
... SSUA that accepts the current image selection for subsequent reboots. Figure 45 presents interactions between the Control Plane (SSUM, image repository) and Data Plane (NPU SSUA and BMC) during a remote BMC image upgrade process. January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 159 ...
Page 160
... Figure 45. Remote upgrade of BMC firmware Image Repository (Control Plane) ® Intel NetStructure IXB2850 Packet Processing Boards TPS 160 SSU Manager NPU SSU Agent (Control Plane) SSU Image Get Information Read Image Header Info Read Image Header Data Image Information SSU Image Upgrade ...
Page 161
... All mechanical specifications conform to PICMG 3.0 (AdvancedTCA). Key parameters for Intel NetStructure • Form factor: AdvancedTCA • Dimensions 280 mm x 1.2 inch pitch Figure 46 shows the mechanical layout for IXB28504XGBEFSx boards. Figure 46. IXB28504xGbEFSx board mechanical layout January 2007 Document Number: 05-2443-006 ® ...
Page 162
... Quad Gigabit Ethernet Mezzanine Card Mechanical Specification IXB28504XGBEFSx boards provide 4 x 1000BASE-CX fiber Gigabit Ethernet interfaces. Figure 47 shows the physical arrangement of the Quad Gigabit Ethernet Mezzanine Card, comprising a Media Mezzanine Card (MMC) and a Fiber Media Interface Card (MIC-F), and the physical connections to the baseboard. The MIC-F card provides the fiber connections to the front panel ...
Page 163
... Quad Gigabit Ethernet Mezzanine Card • External Interfaces SFF 1000BASE-SX (fiber) on the front panel • Internal Interfaces: SPI-3 32-bit MPHY, slow port, I Fabric Interface Card (IXB28504XGBEFSx only) • External Interfaces 1000BASE-BX • Internal Interfaces: SPI-3 4x8 SPHY, slow port, I PCI Mezzanine Card (PMC) Site • ...
Page 164
... Intel field failure data for a similar product, to reflect performance in the field. The MTBF for IXB2850 boards are as follows: • IXB28504XGBEFSx - 353 K hours 12.5.2 MTTR The target Mean Time to Repair (MTTR) for IXB2850 boards is 1 hour for a staffed CO, with replacement boards on-site ...
Page 165
... RJ45 and RS-232 ports (DB9 female plug) for two serial connections. The cable is used for IXB2850 boards to access the Network Processor (NP) or the Intelligent Platform Management Controller (IPMC). Note: The serial console cable must be shielded with a capacitance that does not exceed a value of 2500pF ...
Page 166
... DB9 pin numbers not shown have no connection. Note: The cabling connections in when only that DB9 is used. When both DB9 connectors are used, full model signaling is not available. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 166 Signal DB9 UART #0 Pin TXD ...
Page 167
... Intel NetStructure ® • Intel IXP2850 network processor A high-performance, multi-threaded network processor that encompasses 16 RISC- based microengines and an embedded Intel XScale ® • Intel IXF1104 This Quad Gigabit Ethernet MAC Controller is connected to the NPU through the Media Access Module (for packet transmission/reception) and through the slow port for device configuration and management. Possible IXF1104 chip configurations: — ...
Page 168
... The crosspoint switch is implemented using an Analog Devices* Asynchronous Digital crosspoint switch, AD8152. This chip allows flexible mapping of board Gigabit Ethernet MAC ports to AdvancedTCA fabric interface channels ports. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 168 IXB2850—Component Technology January 2007 ...
Page 169
... If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/ RMA number to place on the outer package of the product. Intel cannot accept any product without a DRA/RMA number on the package. 14.1.1 ...
Page 170
... Direct Return Authorization (DRA) for repair requests, contact the JPSS Repair center. E-mail address: sugiyamakx@intel.co.jp Telephone No.: 81-298-47-8920 Fax No.: 81-298-47-5468 Office Hours: Monday - Friday 0830-1730 Japan time ® Intel NetStructure IXB2850 Packet Processing Boards TPS 170 IXB2850—Return Material Authorization address: January 2007 ...
Page 171
... Product Code Summary Table 66 presents the product codes. Table 66. Product code summary Product Code IXB28504XGBEFS IXB28504XGBEFSW IXB28504XGBEFSR IXB3GDEBUGCABLE January 2007 Document Number: 05-2443-006 ® product for service is in the following MM Number AdvancedTCA line card: ® • Intel IXP2850 network processor 870497 • ...
Page 172
... Electromagnetic Compatibility (EMC) immunity: • CISPR24/EN55024 • EN300386 Network Equipment Building System (NEBS) compliance: • Testing to Level 3. A report documenting the tests and results is available on request. Contact your Intel representative for more information. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 172 IXB2850— ...
Page 173
... R&TTE Directive does not require explicit declaration of conformity to EMC and Low Voltage Directives, above conditions must also be met to satisfy the safety and EMC requirements of the R&TTE Directive. January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 173 ...
Page 174
... Intel Declarations of Conformity for the products covered by this notice can be found under the “Network Building Blocks” heading at litcentr/ce_docs Manufacturer's office in European Union: Intel Corporation (UK) Ltd. Pipers Way Swindon, Wiltshire SN3 1RJ UK Tel: +44 (0)1793 403000 Fax: +44 (0)1793 641440 ® Intel NetStructure ...
Page 175
... All adjustments have been made at the factory prior to shipment of the devices. No maintenance or alteration to the device is required. Do not tamper with or modify the performance of the device. January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 175 ...
Page 176
... IPMI 1.5 - www.intel.com/design/servers/ipmi • FRU 1.0 - www.intel.com/design/servers/ipmi • Wired for Management Baseline 2.0 - • RedBoot* User's Guide - redboot-guide.html ® Intel NetStructure IXB2850 Packet Processing Boards TPS 176 www.picmg.org www.intel.com/design/servers/ipmi http://sources.redhat.com/ecos/docs-latest/redboot/ IXB2850—Related Documentation January 2007 Document Number: 05-2443-006 ...
Page 177
... Gigabit Media Independent Interface General Purpose Input Output General Public License High Availability Institute of Electrical and Electronics Engineers Internet Exchange Key Intelligent Platform Management Controller Intelligent Platform Management Interface Joint Test Action Group Keyboard Controller Style Light Emitting Diode Linux Support Package ...
Page 178
... Slow port SPHY SPI SRAM SSU SSUA SSUM TCAM UART VCXO ® Intel NetStructure IXB2850 Packet Processing Boards TPS 178 Mean Time Between Failures Memory Technology Device Network Processor Optical Carrier Operating System Peripheral Component Interconnect Physical device PCI Mezzanine Card ...
Page 179
... Bring up an Ethernet link on the Base Interface Display available Ethernet ports Change default Ethernet port Execute an image with MMU off Fill memory Create an image in the Flash Image System (FIS) directory Intel NetStructure prompt. The RedBoot> Refer to Section A.2.1 Section A.2.2 Section A.2.3 Section A ...
Page 180
... Read and show a configuration space of the specified device. Shows entire PCI configuration if no arguments are provided. Show the result of the PCI bus scanning and base address (BAR) association process Show internal PCI controller registers of the Intel network processor Scan the PCI bus for devices Verify network connectivity ...
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... Document Number: 05-2443-006 Description Set the POST verbose level and internal UART baud rate Perform and show the results of the PCI Ethernet (Intel 82546 Dual Port Gigabit Ethernet Controller) tests Perform and show the results of the slow port Ethernet tests Perform and show the results of the General Purpose I/0 ...
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... Example alias test “this is a test machine” A.2.2 alignment Manage static alignment for Media Switch Fabric (MSF) configuration. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 182 IXB2850—Boot Monitor Console Commands Description Run the previously loaded Linux kernel image ...
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... Enables the data and instruction caches • off - Disables the data and instruction caches Note parameter is specified, the current cache settings are displayed. Example cache on cache January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 183 ...
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... All unknown records are dumped in binary format. Syntax cfg read [-c <component>] Parameters • -c <component> component to read the configuration from: — Baseboard ® Intel NetStructure IXB2850 Packet Processing Boards TPS 184 IXB2850—Boot Monitor Console Commands January 2007 Document Number: 05-2443-006 ...
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... The component to change/assign a serial number to: — Baseboard — db1 - Media mezzanine card 1 (not used on IXB2850 boards) — db2 - Media mezzanine card 2 — Adjunct processor card January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 185 ...
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... The component to change/assign a serial number to: — Baseboard — db1 - Media mezzanine card 1 (not used on IXB2850 boards) — db2 - Media mezzanine card 2 — Adjunct processor card ® Intel NetStructure IXB2850 Packet Processing Boards TPS 186 IXB2850—Boot Monitor Console Commands cfg hw_version command ...
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... The start of the memory range to compute a checksum. It must be a four byte aligned address. • -l <length> - The length of the memory to compute. It must be at least four bytes and a number that is a multiple of four. January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 187 ...
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... Media mezzanine card 1 (not used on IXB2850 boards) — Media mezzanine card 2 — Media interface card 1 (not used on IXB2850 boards) — Media interface card 2 • -b <data_address> - Base address ® Intel NetStructure IXB2850 Packet Processing Boards TPS 188 IXB2850—Boot Monitor Console Commands Section 11.3.1, “Local Software Upgrade 137 ...
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... A.2.19 eeprom_cksum Calculate and write EEPROM checksum. Syntax eeprom_cksum Example eeprom_cksum A.2.20 eth linkDown Bring down an Ethernet link on a port on the Base Interface. Syntax eth linkDown <interface_name> January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 189 ...
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... Execute an image with MMU off. Syntax exec [-w <timeout>] [-b <load addr> [-l <length>] [-r <ramdisk addr> [-s <ramdisk length>] [-c <kernel command line>] [<entry_point>] [-p <kernel params address>] ® Intel NetStructure IXB2850 Packet Processing Boards TPS 190 IXB2850—Boot Monitor Console Commands January 2007 Document Number: 05-2443-006 ...
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... Address of flash area to be occupied (the default value is the first available block that is large enough) January 2007 Document Number: 05-2443-006 load command to load the file into ® Intel NetStructure IXB2850 Packet Processing Boards TPS 191 ...
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... Displays areas of flash memory that are currently not in use. A block containing non- erased content is considered in use. Syntax fis free Example fis free ® Intel NetStructure IXB2850 Packet Processing Boards TPS 192 IXB2850—Boot Monitor Console Commands -l 0x100000 January 2007 Document Number: 05-2443-006 ...
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... Compute and print the checksum of the image after it has been loaded • Decompress gzipped image while copying it to RAM • name - The name of the file as shown in the FIS directory • Read the flash in 32-bit mode January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 193 ...
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... Parameters • -b <data_address> - Address of the data to be written to flash • -l <length> - Length of the flash area to be occupied (this value may be calculated based on the load ® Intel NetStructure IXB2850 Packet Processing Boards TPS 194 IXB2850—Boot Monitor Console Commands -l 0x1E0000 command. ...
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... Media mezzanine card 2 — Adjunct processor card — mic1 - Media interface card 1 (not used on IXB2850 boards) — mic2 - Media interface card 2 — fic - Fabric interface card January 2007 Document Number: 05-2443-006 -l 0x100000 -f 0x90200000 Intel NetStructure ® IXB2850 Packet Processing Boards TPS 195 ...
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... The command is rejected if the specified record is the last remaining record in the FRU. Example fru delmrecord - ® Intel NetStructure IXB2850 Packet Processing Boards TPS 196 IXB2850—Boot Monitor Console Commands January 2007 Document Number: 05-2443-006 ...
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... New data to be placed in the FRU record: — In ASCII mode possible to write the data directly. If spaces are required, the text must be enclosed in parentheses. — In HEX mode, the format is: 00:11:22:33: ... :EE:FF January 2007 Document Number: 05-2443-006 ® Intel NetStructure IXB2850 Packet Processing Boards TPS 197 ...
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... Messaging” on page • Event data. One of the following: — {npu_boot|post_result|img_error|boot_complete}. See “data 2” in “IPMI event data for boot class” on page ® Intel NetStructure IXB2850 Packet Processing Boards TPS 198 IXB2850—Boot Monitor Console Commands command must be issued to store the changes in non- 01" ...
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... Ethernet is ready to download code. Syntax net init Example net init January 2007 Document Number: 05-2443-006 Table 53, “IPMI event data for the POST class” on Table 54, “IPMI event data for the diagnostics 117. Intel NetStructure Table 52, Table 53 and ® IXB2850 Packet Processing Boards TPS 199 ...
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... Therefore only necessary to specify all the parameters when accessing the configuration space of the given PCI device for the first time. Subsequent access to the same device requires the <offset> parameter only. ® Intel NetStructure IXB2850 Packet Processing Boards TPS 200 IXB2850— ...