IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 246

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

C.2.25
Intel NetStructure
TPS
246
®
Syntax
t gpio option loop
Parameters
Example
t gpio l
t i2c
Perform I
lines. The bus is used to read DDRAM EEPROM content.
Syntax
t i2c w dev addr data
t i2c t dev addr data
t i2c p dev addr size
t i2c c dev addr data
t i2c r dev addr count
t i2c s dev addr count
t i2c a dev
t i2c u mem_size
t i2c v mem_size
Parameters
• option- indicates the test to perform. Can be set as follows:
• loop- specifies the number of times the test is performed (default is 1)
• option- indicates the test to perform. Can be set as follows:
• dev- I
• addr- address in I
• size- page size used in test (1-20)
IXB2850 Packet Processing Boards
— d- GPIO detection test
— r- GPIO register test
— e- GPIO edge detection test
— l- GPIO level detection test
— a- all GPIO tests
— h- help
— w- I
— t- write check test
— p- I
— c- I
— r- I
— s- I
— a- all I
— h- help
— u- update DDRAM EEPROM content with specified mem_size
— v- check DDRAM EEPROM content with specified mem_size
2
2
C bus tests. The I
C device address on the bus (0-7)
2
2
2
2
2
C random read-only test
C current read test
C sequential read test
C page write test
C write-only command
2
C read-only tests
2
C device (0-FFF)
2
C bus is a software-emulated bus that uses two GPIO
Document Number: 05-2443-006
IXB2850—Diagnostics
January 2007