IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 116

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Table 52.
Table 53.
Intel NetStructure
TPS
116
®
The Event Data 2 and Event Data 3 fields contain additional information about events
belonging to the appropriated event class. The
Data 2 and Event Data 3 fields for the Boot class used by the NPU acting as sensor.
IPMI event data for boot class
Table 53
class used by the NPU acting as sensor. These IPMI events messages are generated by
POST.
IPMI event data for the POST class
Data 2
(Event)
00h – Boot started
01h – POST result
02h – Run-time
image error
03h – Boot
completed
Data 2
(Event)
00h – UART
01h – DRAM
02h – QDR SRAM
04h – PCI
05h – BMC
06h – Slow port
Ethernet
07h – PCI Ethernet
08h – ME#0
to
17h – ME#15
18h – Slow port
19h – Interrupts
1Ah – XScale core
1Bh – MSF
1Ch – GPIO
IXB2850 Packet Processing Boards
gives the contents of the Event Data 2 and Event Data 3 fields for the POST
Data 3
(Event Additional
Information)
Reset type:
POST result:
Not used (FFh)
Not used (FFh)
Data 3
(Additional
Information)
Test ID / UART#
Test ID
Test ID
Test ID / Bridge#
Test ID
Test ID
Test ID / Port#
Test ID / Thread#
Test ID
Test ID
Test ID
Test ID
Test ID
• 00h – Hard reset
• 01h – Soft reset
• 00h – Pass
• 01h – Failed
Description
UART POST errors. Test IDs (4 MSb) and UART numbers are listed
in
DRAM POST errors. Test IDs (8 bits) are listed in
“Memory POST” on page
QDR SRAM POST errors. Test IDs (8 bits) are listed in
B.1.2, “Memory POST” on page
PCI POST errors. Test IDs (4 MSb) are listed in
POST” on page
BMC POST errors. Test IDs (8 bits) are listed in
“BMC POST” on page
Slow port Ethernet POST errors. Test IDs (8 bits) are listed in
Section B.1.5, “Slow Port Ethernet POST” on page
PCI Ethernet POST errors. Test IDs (4 MSb) are listed in
B.1.6, “PCI Ethernet POST” on page
start with 0.
Microengines POST errors. Test IDs (4 MSb) are listed in
B.1.7, “Microengines POST” on page
start with 0.
Slow port POST errors. Test IDs (8 bits) are listed in
B.1.5, “Slow Port Ethernet POST” on page
Interrupts POST errors. Test IDs (8 bits) are listed in
B.1.9, “Interrupt POST” on page
XScale core POST errors. Test IDs (8 bits) are listed in
B.1.10, “XScale Core POST” on page
MSF POST errors. Test IDs (8 bits) are listed in
“MSF POST” on page
GPIO POST errors. Test IDs (8 bits) are listed in
“General Purpose I/O (GPIO) POST” on page
Description
Event generated by the Boot Monitor during startup procedure.
Event generated by the Boot Monitor after POST execution. This
event message contains overall POST result.
Event generated by the Boot Monitor if no run-time image can
be loaded and executed. See
page 113
Event generated by the BMC Agent during startup. See
9.6.10.1, “BMC Agent Startup Activity” on page 127
Section B.1.1, “UART POST” on page
for details.
Table 52
224. PCI bridge numbers (4LSb) start with 0.
226.
224.
IXB2850—Network Processor Firmware
224.
gives contents of the Event
Section 9.4.4, “Boot Manager” on
224.
226.
Document Number: 05-2443-006
225. Thread numbers (4LSb)
225. Port numbers (4LSb)
226.
223.
225.
226.
Section B.1.3, “PCI
Section B.1.11,
Section B.1.4,
Section B.1.12,
Section B.1.2,
225.
Section
January 2007
Section
Section
for details.
Section
Section
Section
Section