IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 231

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Diagnostics—IXB2850
C.1.5
January 2007
Document Number: 05-2443-006
The tests cases presented in the following table are executed.
The user can specify:
Serial/UART Tests
UART tests verify each line registers as well as interrupt generation and internal
loopback. The tests cases presented in the following table are executed for all UART
devices:
The user can specify which UART should be tested.
Test ID
00h
01h
02h
03h
04h
05h
06h
07h
Test ID
00h
01h
02h
03h
04h
05h
• memory test start address
• size of tested memory block
• data pattern in user defined pattern test
• how many times test is performed (default is 1)
• UART#0 – NPU embedded UART
• UART#1 – first external UART
• UART#2 – second external UART
Description
Walking ones
Walking zeros
Known pattern tests
Address bus test
Incremental test
Unique test
User defined pattern
ECC test – DRAM only
Description
Register access
Non-FIFO polling
Non-FIFO interrupt test
FIFO polling
FIFO interrupt test
Loopback
• DRAM and SRAM:
- 0x5a5a5a5a pattern
- 0xa5a5a5a5 pattern
Intel NetStructure
®
IXB2850 Packet Processing Boards
TPS
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