IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 115

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Network Processor Firmware—IXB2850
9.4.6
Table 50.
9.4.7
Table 51.
January 2007
Document Number: 05-2443-006
Boot Monitor Device Drivers
The Boot Monitor device drivers are described in
Boot monitor device drivers
IPMI Event Messaging
The NPU on an IXB2850 board acts as the CPU sensor and generates events destined
for the BMC SEL or the ShMC. These events have the format given in
Event Data has a format that complies with the IPMI 1.5 specification.
The
Event data 1 field format
Driver
UART device driver
Debug Ethernet device driver
PCI Gigabit Ethernet MAC
device driver
Bits
7:6
5:4
3:0
Table 51
Value
10b
10b
gives the format of the Event Data 1 field.
Description
Indicates that the Event Data 2 field contains an OEM code
Indicates that the Event Data 3 field contains an OEM code
Offset from the Event/Reading Type Code from the SDR describing a given CPU sensor.
This offset has the meaning of the event class. For details, see
format” on page
Description
Used for serial interface configuration and data transmission/reception over
serial interfaces. This driver allows configuration of the following UART
parameters:
Used for the CS8900A Ethernet MAC controller configuration and data
transmission/reception over debug Ethernet interface.
Used for the 82546 Dual Port Gigabit Ethernet Controller configuration and
data transmission/reception over PCI Ethernet interface connected to the
AdvancedTCA base interface.
This driver configures the following devices:
• Speed – default set to 115200 bps
• Data bits – default is 8
• Parity – default is none
• Stop bits – default is 1
• Flow control – default is none
• Marvell* Alaska 1011 Gigabit Ethernet PHY – Sets GBIC mode for
• AD8152 crosspoint switch – Connects the 82546 Dual Port Gigabit
interfaces connected to the AdvancedTCA base interface.
Ethernet Controller to the AdvancedTCA base interface via the Alaska
Gigabit Ethernet PHY according to the E-Keying base interface state.
56.
Intel NetStructure
Table
50.
®
IXB2850 Packet Processing Boards
Table 22, “Processor SDR
Table
51. The
TPS
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