IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 224

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

B.1.2
B.1.3
B.1.4
Intel NetStructure
TPS
224
®
Memory POST
The following memory types are installed and should be tested:
The tests cases presented in the following table are executed.
PCI POST
The NPU is the PCI host, so it performs the main PCI configuration. These tests check
for the presence of the PCI devices, such as PCI bridges and verify PCI interrupt
generation. The tests cases presented in the following table are executed.
BMC POST
The BMC POST performs IPMI communication tests. The test checks for presence of the
Board Management Controller (BMC) and establish a connection with the BMC through
the UART port. The contents of the ID EEPROMs are read from the BMC to detect the
hardware configuration (there is one ID EEPROM on the baseboard and one on each
Test ID
00h
01h
02h
03h
04h
05h
Test ID
00h
01h
02h
03h
04h
05h
Test ID
00h
01h
• UART#2 - external UART
• DRAM - The remaining part of DRAM (not tested by ROM code) is tested in the
• SRAM - This is a “quick” version of the test, where only one location of each 4K
IXB2850 Packet Processing Boards
second phase of POST. This is a ‘quick’ version of the test, where only one location
of each 4K block of memory is tested (pattern test). Note that a long DRAM test
(pattern test of each memory location) is available from Boot Monitor’s console.
block of memory is tested (pattern test). A long SRAM test (pattern test of each
memory location) is available from Boot Monitor’s console. Note that this applies to
all four SRAM controllers supporting SRAM installed on baseboard.
Description
Walking ones
Walking zeros
Known pattern tests:
Address bus test
Incremental test
Unique test
Description
Device scan on PCI bus – all PCI devices board presence checking
PCI interrupt test
Description
Register access
Non-FIFO polling
Non-FIFO interrupt test
FIFO polling
FIFO interrupt test
Loopback
• DRAM and SRAM:
- 0x5a5a5a5a pattern
- 0xa5a5a5a5 pattern
Document Number: 05-2443-006
IXB2850—Power On Self Test
January 2007