PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 97

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

the P can write a static 8-bit value to a downstream time slot which is then transmitted
repeatedly in each frame until a new value is loaded. In upstream direction, the P can
read the received 8-bit value whenever required, no interrupts being generated.
The "pre-processed channel" option must always be applied to two consecutive time
slots. The first of these time slots must have an even time slot number. If two time- slots
are declared as "pre-processed channels", the first one can be accessed by the monitor/
feature control handler, which gives access to the frame via a 16-byte FIFO. Although
this function is mainly intended for IOM- or SLD-applications, it could also be used to
transmit or receive a "burst" of data to or from a 64-kbit/s channel. The second pre-
processed time slot, the odd one, is also accessed by the P. In downstream direction
a 4-, 6- or 8-bit static value can be transmitted. In upstream direction the received 8-bit
value can be read. Additionally, a change detection mechanism will generate an interrupt
upon a change in any of the selected 4, 6 or 8 bits.
Pre-processed channels are usually programmed after Control Memory (CM) reset
during device initialization. Resetting the CM sets all CFI time slots to unassigned
channels (CM code '0000'). Of course, pre-processed channels can also be initialized or
re-initialized in the operational phase of the device.
To program a pair of pre-processed channels the correct code for the selected handling
scheme must be written to the CM. Figure 48 gives an overview of the available pre-
processing codes and their application. For further detail, please refer to chapter 5.5 of
the EPIC-1 Application Manual.
Sub Time Slot Switching
Sub time slot positions at the PCM-interface can be selected at random, i.e. each single
PCM time slot-may contain any mixture of 2- and 4-bit sub time slots. A PCM time slot
may also contain more than one sub time slot. On the CFI however, two restrictions must
be observed:
– Each CFI time slot may contain one and one only sub time slot.
– The sub-slot position for a given bandwidth within the time slot is fixed on a per port
For more detailed information on sub-channel switching please refer to chapter 5.4.2.
Switching paths 3 and 4 of figure 47 can be realized for all available time slots. Path 3
can be implemented by defining the corresponding CFI time slots as " P-channels" or
as "pre-processed channels".
Each single time slot can individually be declared as " P-channel". If this is the case,
Note: To operate the D-channel arbiter, an IOM-2 configuration with central-, or
Semiconductor Group
P-Transfer
basis.
decentral D-channel handling should be programmed. With the D-channel arbiter
enabled, D-channel bits are handled by the SACCO-A.
97
Operational Description
PEB 20550
PEF 20550
01.96