PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 230

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

PEB 20550
PEF 20550
Application Hints
CFI Bit Timing
In CFI modes 0, 1 and 2, the rising or falling CRCL clock edge can be selected for
transmitting and sampling the data.
In CFI mode 3, the rising or falling CRCL clock edge can be selected for transmitting the
data, the sampling of data however must always be done with the falling edge of CRCL
(CRR = 0).
If CMD2:CXF = 0 (CFI Transmit on Falling edge), the data is transmitted with the rising
CRCL edge, if CXF = 1, the data is transmitted with the next following falling edge of
CRCL.
If CMD2:CRR = 0 (CFI Receive on Rising edge), the data is sampled with the falling
CRCL edge, if CRR = 1, the data is sampled with the next following rising edge of CRCL.
The relationship between the framing and clock signals and the CFI bit stream on DD#
and DU# for CTAR = 02
and CBSR = 20
are illustrated in figure 78 and figure 79.
H
H
Semiconductor Group
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