PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 187

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

AS2..0
PAD1..0
CHAD2..0 Channel Address.
4.8.3
Access in demultiplexed P-interface mode:
SCV7..0
4.8.2
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
bit 7
SCV7
AS2
Arbiter State Register (ASTATE)
Suspend Counter Value Register (SCV)
Arbiter (receive channel selector) State:
000 : suspended
100 : full selection
011 : limited selection
001 : expect frame
010 : receive frame
Port Address.
The related frame was received on IOM-port PAD1..0
The related frame was received in IOM-channel CHAD2..0.
Suspend Counter Value.
The value (SCV7..0 + 1)
analyzed in the state "expect frame" before the arbiter enters the state
suspended state and an interrupt is issued.
Min.: 32
SCV6
AS1
H
H
D-bits (16 frames), max: 8192 D-bits.
SCV5
AS0
SCV4
PAD1
32 defines the number of D-bits which are
187
SCV3
PAD0
read
read
read/write
read/write
Detailed Register Description
CHAD2
SCV2
address: 62
address: 61
address: C2
address: C4
CHAD1
SCV1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
CHAD0
SCV0
01.96