PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 16

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

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Semiconductor Group
-Processor Interface
Pin Definitions and Functions
Symbol
CSE
CSS
WR,
R/W
RD, DS
AD0, D0
AD1, D1
AD2, D2
AD3, D3
AD4, D4
AD5, D5
AD6, D6
AD7, D7
ALE
Input (I)
Output (O)
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Function
Chip Select EPIC-1; active low. A "low" on this line
selects all registers (excluding the SACCO-
registers) for read/write operations.
Chip Select SACCO; active low. A "low" on this
line selects the SACCO-registers for read/write
operations.
Write, active low, Siemens/Intel bus mode.
When "low", a write operation is indicated.
Read/Write, Motorola bus mode.
When "high" a valid P-access identifies a read
operation, when "low" it identifies a write access.
Read, active low, Siemens/Intel bus mode.
When "low" a read operation is indicated.
Data Strobe, Motorola bus mode.
A rising edge marks the end of a read or write
operation.
Address/Data Bus; multiplexed bus mode.
Transfers addresses from the P-system to the
ELIC and data between the P and the ELIC.
Data Bus; demultiplexed bus mode.
Transfers data between the P and the ELIC.
When driving data the pins have push pull
characteristic, otherwise they are in the state
high impedance.
Address Latch Enable
ALE controls the on chip address latch in
multiplexed bus mode. While ALE is "high", the
latch is transparent. The falling edge latches the
current address. During the first read/write access
following reset ALE is evaluated to select the bus
mode.
16
PEB 20550
PEF 20550
Overview
01.96