PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 205

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Table 28
Formulas to Calculate the PCM Frame Offset Upstream (TxD#)
PCM Mode
0
1, 3
2
Examples
1) In PCM mode 0, with a frame consisting of 32 timeslots, the following timing
Figure 62
Timing PCM Frame Offset for Example 1
Semiconductor Group
PFS
PDC
TxD#
RxD#
Required
Time-Slot
and Bit
Offset
relationship between the framing signal and the data signals is required:
256
0
Offset Upstream, POFU, PCSR
OFU9 … 2 = (BNU + 23)
OFU9 … 1 = (BNU + 47)
OFU9 … 0 = (BNU + 95)
Bit 7
1
1
Start of Internal Frame
BNU
BND
Bit 6
2
Bit 5
3
Bit 4
Time-Slot 0
4
Bit 3
mod BPF
mod BPF
mod BPF
5
205
Bit 2
6
Bit 1
7
Bit 0
8
Remarks
PCSR:OFU1 … 0 = 0
PCSR:OFU0 = 0
–
9
10
Application Hints
PCSR
PCSR
PMOD PSM = 0
PEB 20550
PEF 20550
:
:
:
URE
DRE = 0
ITT08041
=
1
01.96