PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 201

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Table 25
PCM Mode
0
1, 3
2
Table 26
Formulas to Calculate the PBNR Value
PCM Mode
0
1, 3
2
In PCM mode 1 a PCM frame consisting of 24 timeslots would require a setting of
PBNR = (24
In PCM mode 2 a PCM frame consisting of 64 timeslots would require a setting of
PBNR = (64
Note: There is a mode dependent restriction on the possible number of bits per frame
Also refer to table 25.
This number of bits must be programmed to PBNR:BNF7 … 0 as indicated in table 26.
The externally applied frame synchronization pulse PFS resets the internal PCM timeslot
and bit counters. The value programmed to PBNR is internally used to reset the PCM
timeslot and bit counters so that these counters always count modulo the actual number
of bits per frame even in the absence of the external PFS pulse. Additionally, the PFS
period is internally checked against the PBNR value. The result of this comparison is
displayed in the PCM Synchronization Status bit (STAR:PSS). Also, refer to
chapter 5.8.3.
Examples
In PCM mode 0 a PCM frame consisting of 32 timeslots would require a setting of
PBNR = 32 8 – 1 = 255
Semiconductor Group
BPF:
8 – 2)/2 = 95
8 – 4)/4 = 127
D
D
= FF
D
= 5F
= 7F
Possible Values for BNF
BPF must be modulo 32
BPF must be modulo 64
BPF must be modulo 128
PBNR:BNF7 … 0(Hex)
BPF7 … 0 = BPF – 1
BPF7 … 0 = (BPF – 2)/2
BPF7 … 0 = (BPF – 4)/4
H
.
H
.
H
.
201
Application Hints
PEB 20550
PEF 20550
01.96