PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 28

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

On an U
terminal. The T-channel is a sub channel of the U
s.
In the subscriber terminal the control channel is included again in the IOM-2 protocol.
Depending on the terminal configuration two alternatives can be selected in the terminal
transceiver device.
The blocked/available information is translated directly into the S/G-bit (Stop/Go) when
no subsequent transceiver circuit is present in the terminal. The S/G-bit is evaluated by
the terminal HDLC-controller ICC. It stops data transmission immediately when the S/
G-bit is set to 1.
Figure 8
Control Channel Implementation with IBC (PEB 2095) as Line Card Transceiver
The control channel is unidirectional and forwards the status information of the
corresponding D-channel (blocked or available) towards the subscriber terminal.
Different existing channel structures are used to implement the control channel between
the HDLC-controllers on the line card and in the subscriber terminal.
Control Channel Implementation on the U
the MR-bit, depending on the connected layer-1 device (OCTAT-P -> C/I channel, IBC
-> MR-bit).
The U
Semiconductor Group
PN
(optional)
-transceiver uses the T-channel to transmit the control channel information to the
ICC
PN
-line card, the control channel is either integrated in the C/I-channel or uses
S/G = 1
S/G = 0
S/G
Blocked
Available
HDLC Controller
DSAC-P
Trans-
ceiver
U
p0
T = 0
T = 1
28
PN
T
Blocked
Available
-Interface
PN
-interface with a bandwidth of 2 kbit/
IBC
MR = 0
MR = 1
MR
Blocked
Available
PEB 20550
ELIC
PEF 20550
Overview
R
ITS05809
01.96